video/drm: edp: code style cleanup and fixes
Change-Id: I7ae761ca7a493e72fc4b4ed55f6cb2aa40a7cbfa Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
Jianhong Chen
parent
95351b7a0e
commit
9c3b19b6a2
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@ -136,7 +136,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
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pll_tries = 0;
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while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
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pr_err("Wait for PLL lock timed out\n");
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dev_err(dp->dev, "Wait for PLL lock timed out\n");
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return -ETIMEDOUT;
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}
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@ -334,7 +334,7 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
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if (retval)
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return retval;
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pr_info("Link Training Clock Recovery success\n");
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dev_info(dp->dev, "Link Training Clock Recovery success\n");
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dp->link_train.lt_state = EQUALIZER_TRAINING;
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} else {
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for (lane = 0; lane < lane_count; lane++) {
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@ -354,7 +354,7 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
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if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
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voltage_swing == VOLTAGE_LEVEL_3 ||
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pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
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pr_err("CR Max reached (%d,%d,%d)\n",
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dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
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dp->link_train.cr_loop[lane],
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voltage_swing, pre_emphasis);
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analogix_dp_reduce_link_rate(dp);
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@ -414,17 +414,15 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
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/* traing pattern Set to Normal */
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analogix_dp_training_pattern_dis(dp);
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pr_info("Link Training success!\n");
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printf("Link Training success!\n");
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analogix_dp_get_link_bandwidth(dp, ®);
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dp->link_train.link_rate = reg;
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pr_debug("final bandwidth = %.2x\n",
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dp->link_train.link_rate);
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analogix_dp_get_lane_count(dp, ®);
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dp->link_train.lane_count = reg;
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pr_debug("final lane count = %.2x\n",
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dp->link_train.lane_count);
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printf("final link rate = 0x%.2x, lane count = 0x%.2x\n",
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dp->link_train.link_rate, dp->link_train.lane_count);
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/* set enhanced mode if available */
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analogix_dp_set_enhanced_mode(dp);
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@ -437,7 +435,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
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dp->link_train.eq_loop++;
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if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
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pr_err("EQ Max loop\n");
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dev_dbg(dp->dev, "EQ Max loop\n");
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analogix_dp_reduce_link_rate(dp);
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return -EIO;
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}
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@ -480,9 +478,9 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
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*lane_count = DPCD_MAX_LANE_COUNT(data);
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}
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static void analogix_dp_init_training(struct analogix_dp_device *dp,
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enum link_lane_count_type max_lane,
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int max_rate)
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static int analogix_dp_init_training(struct analogix_dp_device *dp,
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enum link_lane_count_type max_lane,
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int max_rate)
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{
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/*
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* MACRO_RST must be applied after the PLL_LOCK to avoid
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@ -497,15 +495,13 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
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if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
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(dp->link_train.link_rate != DP_LINK_BW_2_7) &&
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(dp->link_train.link_rate != DP_LINK_BW_5_4)) {
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pr_err("Rx Max Link Rate is abnormal :%x !\n",
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dp->link_train.link_rate);
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dp->link_train.link_rate = DP_LINK_BW_1_62;
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dev_err(dp->dev, "failed to get Rx Max Link Rate\n");
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return -ENODEV;
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}
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if (dp->link_train.lane_count == 0) {
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pr_err("Rx Max Lane count is abnormal :%x !\n",
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dp->link_train.lane_count);
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dp->link_train.lane_count = (u8)LANE_COUNT1;
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dev_err(dp->dev, "failed to get Rx Max Lane Count\n");
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return -ENODEV;
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}
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/* Setup TX lane count & rate */
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@ -516,6 +512,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
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/* All DP analog module power up */
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analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
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return 0;
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}
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static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
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@ -530,17 +528,17 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
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case START:
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retval = analogix_dp_link_start(dp);
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if (retval)
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pr_err("LT link start failed!\n");
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dev_err(dp->dev, "LT link start failed!\n");
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break;
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case CLOCK_RECOVERY:
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retval = analogix_dp_process_clock_recovery(dp);
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if (retval)
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pr_err("LT CR failed!\n");
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dev_err(dp->dev, "LT CR failed!\n");
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break;
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case EQUALIZER_TRAINING:
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retval = analogix_dp_process_equalizer_training(dp);
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if (retval)
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pr_err("LT EQ failed!\n");
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dev_err(dp->dev, "LT EQ failed!\n");
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break;
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case FINISHED:
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training_finished = 1;
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@ -549,8 +547,6 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
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return -EREMOTEIO;
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}
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}
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if (retval)
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pr_err("eDP link training failed (%d)\n", retval);
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return retval;
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}
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@ -558,24 +554,25 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
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static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
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u32 count, u32 bwtype)
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{
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int i;
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int retval;
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int ret;
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for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
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analogix_dp_init_training(dp, count, bwtype);
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retval = analogix_dp_sw_link_training(dp);
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if (retval == 0)
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break;
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udelay(110);
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ret = analogix_dp_init_training(dp, count, bwtype);
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if (ret < 0) {
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dev_err(dp->dev, "failed to init training\n");
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return ret;
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}
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return retval;
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ret = analogix_dp_sw_link_training(dp);
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if (ret < 0) {
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dev_err(dp->dev, "failed to do sw link training\n");
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return ret;
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}
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return 0;
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}
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static int analogix_dp_config_video(struct analogix_dp_device *dp)
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{
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int retval = 0;
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int timeout_loop = 0;
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int done_count = 0;
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@ -584,7 +581,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
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analogix_dp_set_video_color_format(dp);
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if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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pr_err("PLL is not locked yet.\n");
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dev_err(dp->dev, "PLL is not locked yet.\n");
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return -EINVAL;
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}
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@ -593,7 +590,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
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if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
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break;
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if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
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pr_err("Timeout of video streamclk ok\n");
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dev_err(dp->dev, "Timeout of video streamclk ok\n");
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return -ETIMEDOUT;
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}
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@ -627,17 +624,14 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
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done_count = 0;
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}
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if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
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pr_err("Timeout of video streamclk ok\n");
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dev_err(dp->dev, "Timeout of video streamclk ok\n");
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return -ETIMEDOUT;
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}
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udelay(1001);
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}
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if (retval != 0)
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pr_err("Video stream is not detected!\n");
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return retval;
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return 0;
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}
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static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
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@ -698,7 +692,6 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
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{
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unsigned char *edid = dp->edid;
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unsigned int extend_block = 0;
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unsigned char sum;
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unsigned char test_vector;
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int retval;
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@ -724,15 +717,11 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
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EDID_HEADER_PATTERN,
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EDID_BLOCK_LENGTH,
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&edid[EDID_HEADER_PATTERN]);
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if (retval != 0) {
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pr_err("EDID Read failed!\n");
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return -EIO;
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}
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sum = analogix_dp_calc_edid_check_sum(edid);
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if (sum != 0) {
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pr_err("EDID bad checksum!\n");
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return -EIO;
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}
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if (retval < 0)
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return retval;
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if (analogix_dp_calc_edid_check_sum(edid))
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return -EINVAL;
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/* Read additional EDID data */
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retval = analogix_dp_read_bytes_from_i2c(dp,
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@ -740,15 +729,11 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
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EDID_BLOCK_LENGTH,
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EDID_BLOCK_LENGTH,
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&edid[EDID_BLOCK_LENGTH]);
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if (retval != 0) {
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pr_err("EDID Read failed!\n");
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return -EIO;
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}
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sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
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if (sum != 0) {
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pr_err("EDID bad checksum!\n");
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return -EIO;
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}
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if (retval < 0)
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return retval;
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if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]))
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return -EINVAL;
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analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
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&test_vector);
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@ -761,21 +746,18 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
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DP_TEST_EDID_CHECKSUM_WRITE);
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}
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} else {
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pr_info("EDID data does not include any extensions.\n");
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dev_info(dp->dev,
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"EDID data does not include any extensions.\n");
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/* Read EDID data */
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retval = analogix_dp_read_bytes_from_i2c(dp,
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I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
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EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
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if (retval != 0) {
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pr_err("EDID Read failed!\n");
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return -EIO;
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}
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sum = analogix_dp_calc_edid_check_sum(edid);
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if (sum != 0) {
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pr_err("EDID bad checksum!\n");
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return -EIO;
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}
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if (retval < 0)
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return retval;
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if (analogix_dp_calc_edid_check_sum(edid))
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return -EINVAL;
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analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
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&test_vector);
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@ -787,7 +769,6 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
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}
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}
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debug("EDID Read success!\n");
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return 0;
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}
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@ -819,165 +800,61 @@ retry:
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return retval;
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}
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const struct rockchip_dp_chip_data rk3399_analogix_edp_drv_data = {
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.lcdsel_grf_reg = 0x6250,
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.lcdsel_big = 0 | BIT(21),
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.lcdsel_lit = BIT(5) | BIT(21),
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.chip_type = RK3399_EDP,
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.has_vop_sel = true,
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};
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const struct rockchip_dp_chip_data rk3288_analogix_dp_drv_data = {
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.lcdsel_grf_reg = 0x025c,
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.lcdsel_big = 0 | BIT(21),
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.lcdsel_lit = BIT(5) | BIT(21),
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.chip_type = RK3288_DP,
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.has_vop_sel = true,
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};
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const struct rockchip_dp_chip_data rk3368_analogix_edp_drv_data = {
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.chip_type = RK3368_EDP,
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.has_vop_sel = false,
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};
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static int rockchip_analogix_dp_init(struct display_state *state)
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static int analogix_dp_connector_init(struct display_state *state)
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{
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struct connector_state *conn_state = &state->conn_state;
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const struct rockchip_connector *connector = conn_state->connector;
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const struct rockchip_dp_chip_data *pdata = connector->data;
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struct analogix_dp_device *dp;
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struct analogix_dp_plat_data *plat_data;
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int ret;
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struct analogix_dp_device *dp = dev_get_priv(conn_state->dev);
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dp = malloc(sizeof(*dp));
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if (!dp)
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return -ENOMEM;
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memset(dp, 0, sizeof(*dp));
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plat_data = malloc(sizeof(*pdata));
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if (!plat_data)
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return -ENOMEM;
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dp->reg_base = dev_read_addr_ptr(conn_state->dev);
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dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (dp->grf <= 0) {
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printf("%s: Get syscon grf failed (ret=%p)\n",
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__func__, dp->grf);
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return -ENXIO;
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}
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ret = gpio_request_by_name(conn_state->dev, "hpd-gpios", 0,
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&dp->hpd_gpio, GPIOD_IS_IN);
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if (ret != -ENOENT) {
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printf("%s: Warning: cannot get hpd GPIO: ret=%d\n",
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__func__, ret);
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return ret;
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}
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dp->plat_data = plat_data;
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dp->plat_data->dev_type = ROCKCHIP_DP;
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dp->plat_data->subdev_type = pdata->chip_type;
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/*
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* Like Rockchip DisplayPort TRM indicate that "Main link
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* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
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*/
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dp->video_info.max_link_rate = 0x0A;
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dp->video_info.max_lane_count = 0x04;
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conn_state->private = dp;
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conn_state->type = DRM_MODE_CONNECTOR_eDP;
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conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
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conn_state->color_space = V4L2_COLORSPACE_DEFAULT;
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#if 0
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if (pdata->chip_type == RK3399_EDP) {
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/*
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* reset edp controller.
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*/
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writel(0x20002000, RKIO_CRU_PHYS + 0x444);
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mdelay(10);
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writel(0x20000000, RKIO_CRU_PHYS + 0x444);
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mdelay(10);
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} else if (pdata->chip_type == RK3368_EDP) {
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/* edp ref clk sel */
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writel(0x00010001, RKIO_GRF_PHYS + 0x410);
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/* edp 24m clock domain software reset */
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writel(0x80008000, RKIO_CRU_PHYS + 0x318);
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udelay(20);
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writel(0x80000000, RKIO_CRU_PHYS + 0x318);
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/* edp ctrl apb bus software reset */
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writel(0x04000400, RKIO_CRU_PHYS + 0x31c);
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udelay(20);
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writel(0x04000000, RKIO_CRU_PHYS + 0x31c);
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} else if (pdata->chip_type == RK3288_DP) {
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/* edp ref clk sel */
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writel(0x00100010, RKIO_GRF_PHYS + 0x274);
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/* edp 24m clock domain software reset */
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writel(0x80008000, RKIO_CRU_PHYS + 0x1d0);
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udelay(20);
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writel(0x80000000, RKIO_CRU_PHYS + 0x1d0);
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udelay(20);
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}
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#endif
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analogix_dp_init_dp(dp);
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return 0;
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}
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static void rockchip_analogix_dp_deinit(struct display_state *state)
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{
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/* TODO */
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}
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static int rockchip_analogix_dp_get_edid(struct display_state *state)
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static int analogix_dp_connector_get_edid(struct display_state *state)
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{
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struct connector_state *conn_state = &state->conn_state;
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struct analogix_dp_device *dp = conn_state->private;
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struct analogix_dp_device *dp = dev_get_priv(conn_state->dev);
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int ret;
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ret = analogix_dp_handle_edid(dp);
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if (ret)
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if (ret) {
|
||||
dev_err(dp->dev, "failed to get edid\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_analogix_dp_prepare(struct display_state *state)
|
||||
static int analogix_dp_connector_enable(struct display_state *state)
|
||||
{
|
||||
struct connector_state *conn_state = &state->conn_state;
|
||||
struct crtc_state *crtc_state = &state->crtc_state;
|
||||
const struct rockchip_connector *connector = conn_state->connector;
|
||||
const struct rockchip_dp_chip_data *pdata = connector->data;
|
||||
struct analogix_dp_device *dp = conn_state->private;
|
||||
struct analogix_dp_device *dp = dev_get_priv(conn_state->dev);
|
||||
u32 val;
|
||||
|
||||
if (!pdata->has_vop_sel)
|
||||
return 0;
|
||||
|
||||
if (crtc_state->crtc_id)
|
||||
val = pdata->lcdsel_lit;
|
||||
else
|
||||
val = pdata->lcdsel_big;
|
||||
|
||||
writel(val, dp->grf + pdata->lcdsel_grf_reg);
|
||||
|
||||
debug("vop %s output to edp\n", (crtc_state->crtc_id) ? "LIT" : "BIG");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_analogix_dp_enable(struct display_state *state)
|
||||
{
|
||||
struct connector_state *conn_state = &state->conn_state;
|
||||
struct analogix_dp_device *dp = conn_state->private;
|
||||
int ret;
|
||||
|
||||
if (pdata->has_vop_sel) {
|
||||
if (crtc_state->crtc_id)
|
||||
val = pdata->lcdsel_lit;
|
||||
else
|
||||
val = pdata->lcdsel_big;
|
||||
|
||||
writel(val, dp->grf + pdata->lcdsel_grf_reg);
|
||||
}
|
||||
|
||||
ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
|
||||
dp->video_info.max_link_rate);
|
||||
if (ret) {
|
||||
pr_err("unable to do link train\n");
|
||||
return 0;
|
||||
dev_err(dp->dev, "unable to do link train\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
analogix_dp_enable_scramble(dp, 1);
|
||||
|
|
@ -986,58 +863,116 @@ static int rockchip_analogix_dp_enable(struct display_state *state)
|
|||
|
||||
analogix_dp_init_video(dp);
|
||||
ret = analogix_dp_config_video(dp);
|
||||
if (ret)
|
||||
pr_err("unable to config video\n");
|
||||
if (ret) {
|
||||
dev_err(dp->dev, "unable to config video\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_analogix_dp_disable(struct display_state *state)
|
||||
static int analogix_dp_connector_disable(struct display_state *state)
|
||||
{
|
||||
/* TODO */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct rockchip_connector_funcs rockchip_analogix_dp_funcs = {
|
||||
.init = rockchip_analogix_dp_init,
|
||||
.deinit = rockchip_analogix_dp_deinit,
|
||||
.get_edid = rockchip_analogix_dp_get_edid,
|
||||
.prepare = rockchip_analogix_dp_prepare,
|
||||
.enable = rockchip_analogix_dp_enable,
|
||||
.disable = rockchip_analogix_dp_disable,
|
||||
static const struct rockchip_connector_funcs analogix_dp_connector_funcs = {
|
||||
.init = analogix_dp_connector_init,
|
||||
.get_edid = analogix_dp_connector_get_edid,
|
||||
.enable = analogix_dp_connector_enable,
|
||||
.disable = analogix_dp_connector_disable,
|
||||
};
|
||||
|
||||
static const struct rockchip_connector rk3288_analogix_dp_data = {
|
||||
.funcs = &rockchip_analogix_dp_funcs,
|
||||
.data = &rk3288_analogix_dp_drv_data,
|
||||
static int analogix_dp_probe(struct udevice *dev)
|
||||
{
|
||||
struct analogix_dp_device *dp = dev_get_priv(dev);
|
||||
const struct rockchip_connector *connector =
|
||||
(const struct rockchip_connector *)dev_get_driver_data(dev);
|
||||
const struct rockchip_dp_chip_data *pdata = connector->data;
|
||||
int ret;
|
||||
|
||||
dp->reg_base = dev_read_addr_ptr(dev);
|
||||
dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
if (IS_ERR(dp->grf))
|
||||
return PTR_ERR(dp->grf);
|
||||
|
||||
ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio,
|
||||
GPIOD_IS_IN);
|
||||
if (ret && ret != -ENOENT) {
|
||||
dev_err(dev, "failed to get hpd GPIO: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dp->plat_data.dev_type = ROCKCHIP_DP;
|
||||
dp->plat_data.subdev_type = pdata->chip_type;
|
||||
/*
|
||||
* Like Rockchip DisplayPort TRM indicate that "Main link
|
||||
* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
|
||||
*/
|
||||
dp->video_info.max_link_rate = 0x0A;
|
||||
dp->video_info.max_lane_count = 0x04;
|
||||
|
||||
dp->dev = dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rockchip_dp_chip_data rk3288_edp_platform_data = {
|
||||
.lcdsel_grf_reg = 0x025c,
|
||||
.lcdsel_big = 0 | BIT(21),
|
||||
.lcdsel_lit = BIT(5) | BIT(21),
|
||||
.chip_type = RK3288_DP,
|
||||
.has_vop_sel = true,
|
||||
};
|
||||
|
||||
static const struct rockchip_connector rk3399_analogix_edp_data = {
|
||||
.funcs = &rockchip_analogix_dp_funcs,
|
||||
.data = &rk3399_analogix_edp_drv_data,
|
||||
static const struct rockchip_connector rk3288_edp_driver_data = {
|
||||
.funcs = &analogix_dp_connector_funcs,
|
||||
.data = &rk3288_edp_platform_data,
|
||||
};
|
||||
|
||||
static const struct rockchip_connector rk3368_analogix_edp_data = {
|
||||
.funcs = &rockchip_analogix_dp_funcs,
|
||||
.data = &rk3368_analogix_edp_drv_data,
|
||||
static const struct rockchip_dp_chip_data rk3368_edp_platform_data = {
|
||||
.chip_type = RK3368_EDP,
|
||||
.has_vop_sel = false,
|
||||
};
|
||||
|
||||
static const struct udevice_id rockchip_analogix_dp_ids[] = {
|
||||
static const struct rockchip_connector rk3368_edp_driver_data = {
|
||||
.funcs = &analogix_dp_connector_funcs,
|
||||
.data = &rk3368_edp_platform_data,
|
||||
};
|
||||
|
||||
static const struct rockchip_dp_chip_data rk3399_edp_platform_data = {
|
||||
.lcdsel_grf_reg = 0x6250,
|
||||
.lcdsel_big = 0 | BIT(21),
|
||||
.lcdsel_lit = BIT(5) | BIT(21),
|
||||
.chip_type = RK3399_EDP,
|
||||
.has_vop_sel = true,
|
||||
};
|
||||
|
||||
static const struct rockchip_connector rk3399_edp_driver_data = {
|
||||
.funcs = &analogix_dp_connector_funcs,
|
||||
.data = &rk3399_edp_platform_data,
|
||||
};
|
||||
|
||||
static const struct udevice_id analogix_dp_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3288-dp",
|
||||
.data = (ulong)&rk3288_analogix_dp_data,
|
||||
},{
|
||||
.compatible = "rockchip,rk3399-edp",
|
||||
.data = (ulong)&rk3399_analogix_edp_data,
|
||||
},{
|
||||
.compatible = "rockchip,rk3368-edp",
|
||||
.data = (ulong)&rk3368_analogix_edp_data,
|
||||
}, {}
|
||||
.compatible = "rockchip,rk3288-dp",
|
||||
.data = (ulong)&rk3288_edp_driver_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3368-edp",
|
||||
.data = (ulong)&rk3368_edp_driver_data,
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-edp",
|
||||
.data = (ulong)&rk3399_edp_driver_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rockchip_analogix_dp) = {
|
||||
.name = "rockchip_analogix_dp",
|
||||
U_BOOT_DRIVER(analogix_dp) = {
|
||||
.name = "analogix_dp",
|
||||
.id = UCLASS_DISPLAY,
|
||||
.of_match = rockchip_analogix_dp_ids,
|
||||
.of_match = analogix_dp_ids,
|
||||
.probe = analogix_dp_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct analogix_dp_device),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1068,13 +1068,14 @@ struct analogix_dp_plat_data {
|
|||
};
|
||||
|
||||
struct analogix_dp_device {
|
||||
struct udevice *dev;
|
||||
void *reg_base;
|
||||
void *grf;
|
||||
struct gpio_desc hpd_gpio;
|
||||
struct video_info video_info;
|
||||
struct link_train link_train;
|
||||
struct drm_display_mode *mode;
|
||||
struct analogix_dp_plat_data *plat_data;
|
||||
struct analogix_dp_plat_data plat_data;
|
||||
unsigned char edid[EDID_BLOCK_LENGTH * 2];
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -81,10 +81,10 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
|
|||
reg = SEL_24M | TX_DVDD_BIT_1_0625V;
|
||||
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
|
||||
|
||||
if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP)) {
|
||||
if (dp->plat_data.dev_type == ROCKCHIP_DP) {
|
||||
reg = REF_CLK_24M;
|
||||
if (dp->plat_data->subdev_type == RK3288_DP ||
|
||||
dp->plat_data->subdev_type == RK3368_EDP)
|
||||
if (dp->plat_data.subdev_type == RK3288_DP ||
|
||||
dp->plat_data.subdev_type == RK3368_EDP)
|
||||
reg ^= REF_CLK_MASK;
|
||||
|
||||
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
|
||||
|
|
@ -256,7 +256,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
|
|||
u32 reg;
|
||||
u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
|
||||
|
||||
if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP))
|
||||
if (dp->plat_data.dev_type == ROCKCHIP_DP)
|
||||
phy_pd_addr = ANALOGIX_DP_PD;
|
||||
|
||||
switch (block) {
|
||||
|
|
@ -360,8 +360,9 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
|
|||
|
||||
while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
|
||||
timeout_loop++;
|
||||
if(DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
|
||||
pr_err("failed to get pll lock status\n");
|
||||
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
|
||||
dev_err(dp->dev,
|
||||
"failed to get pll lock status\n");
|
||||
return;
|
||||
}
|
||||
udelay(20);
|
||||
|
|
@ -460,7 +461,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
|
|||
analogix_dp_reset_aux(dp);
|
||||
|
||||
/* Disable AUX transaction H/W retry */
|
||||
if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP))
|
||||
if (dp->plat_data.dev_type == ROCKCHIP_DP)
|
||||
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
|
||||
AUX_HW_RETRY_COUNT_SEL(3) |
|
||||
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
|
||||
|
|
@ -521,9 +522,10 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
|
|||
while (!(reg & RPLY_RECEIV)) {
|
||||
timeout_loop++;
|
||||
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
|
||||
pr_err("AUX CH command reply failed!\n");
|
||||
dev_err(dp->dev, "AUX CH command reply failed!\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
|
||||
udelay(11);
|
||||
}
|
||||
|
|
@ -541,8 +543,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
|
|||
/* Check AUX CH error access status */
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
|
||||
if ((reg & AUX_STATUS_MASK) != 0) {
|
||||
pr_err("AUX CH error happens: %d\n\n",
|
||||
reg & AUX_STATUS_MASK);
|
||||
dev_err(dp->dev,
|
||||
"AUX CH error happens: %d\n", reg & AUX_STATUS_MASK);
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
|
||||
|
|
@ -586,8 +588,6 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
|
|||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
|
||||
pr_debug("%s: Aux Transaction fail!\n", __func__);
|
||||
}
|
||||
|
||||
return retval;
|
||||
|
|
@ -626,8 +626,6 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
|
|||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
|
||||
pr_info("%s: Aux Transaction fail!\n", __func__);
|
||||
}
|
||||
|
||||
/* Read data buffer */
|
||||
|
|
@ -691,9 +689,6 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
|
|||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
|
||||
pr_debug("%s: Aux Transaction fail!\n",
|
||||
__func__);
|
||||
}
|
||||
|
||||
start_offset += cur_data_count;
|
||||
|
|
@ -749,9 +744,6 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
|
|||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
|
||||
pr_debug("%s: Aux Transaction fail!\n",
|
||||
__func__);
|
||||
}
|
||||
|
||||
for (cur_data_idx = 0; cur_data_idx < cur_data_count;
|
||||
|
|
@ -795,10 +787,10 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
|
|||
|
||||
/* Start AUX transaction */
|
||||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval != 0)
|
||||
pr_debug("%s: Aux Transaction fail!\n", __func__);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
|
||||
return retval;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
|
||||
|
|
@ -834,8 +826,6 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
|
|||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
|
||||
pr_debug("%s: Aux Transaction fail!\n", __func__);
|
||||
}
|
||||
|
||||
/* Read data */
|
||||
|
|
@ -894,15 +884,12 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
|
|||
retval = analogix_dp_start_aux_transaction(dp);
|
||||
if (retval == 0)
|
||||
break;
|
||||
|
||||
pr_debug("%s: Aux Transaction fail!\n",
|
||||
__func__);
|
||||
}
|
||||
/* Check if Rx sends defer */
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
|
||||
if (reg == AUX_RX_COMM_AUX_DEFER ||
|
||||
reg == AUX_RX_COMM_I2C_DEFER) {
|
||||
pr_err("Defer: %d\n\n", reg);
|
||||
dev_dbg(dp->dev, "Defer: %d\n\n", reg);
|
||||
defer = 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -1175,21 +1162,16 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
|
|||
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
|
||||
|
||||
if (!(reg & DET_STA)) {
|
||||
pr_debug("Input stream clock not detected.\n");
|
||||
if (!(reg & DET_STA))
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
|
||||
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
|
||||
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
|
||||
pr_debug("wait SYS_CTL_2.\n");
|
||||
|
||||
if (reg & CHA_STA) {
|
||||
pr_debug("Input stream clk is changing\n");
|
||||
if (reg & CHA_STA)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1277,10 +1259,8 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
|
|||
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
|
||||
|
||||
reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
|
||||
if (!(reg & STRM_VALID)) {
|
||||
pr_debug("Input video stream is not detected.\n");
|
||||
if (!(reg & STRM_VALID))
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue