qiurui
/
rv1126-uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: rockchip: px30: Restore sfc frequency after PLL frequency setting 

Change-Id: I261885b027c4c5ba6d94fb228fb04563cb4e0b0e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2020-02-24 10:02:02 +08:00 committed by Jianhong Chen
parent fc722856eb
commit 9bc02da530
1 changed files with 38 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/clk/rockchip/clk_px30.c
View File

@ -587,6 +587,32 @@ static ulong px30_mmc_set_clk(struct px30_clk_priv *priv,
return px30_mmc_get_clk(priv, clk_id);
}
static ulong px30_sfc_get_clk(struct px30_clk_priv *priv, uint clk_id)
{
struct px30_cru *cru = priv->cru;
u32 div, con;
con = readl(&cru->clksel_con[22]);
div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT;
return DIV_TO_RATE(priv->gpll_hz, div);
}
static ulong px30_sfc_set_clk(struct px30_clk_priv *priv,
ulong clk_id, ulong set_rate)
{
struct px30_cru *cru = priv->cru;
int src_clk_div;
src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);
rk_clrsetreg(&cru->clksel_con[22],
SFC_PLL_SEL_MASK | SFC_DIV_CON_MASK,
0 << SFC_PLL_SEL_SHIFT |
(src_clk_div - 1) << SFC_DIV_CON_SHIFT);
return px30_sfc_get_clk(priv, clk_id);
}
static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id)
{
struct px30_cru *cru = priv->cru;
@ -1215,6 +1241,9 @@ static ulong px30_clk_get_rate(struct clk *clk)
case SCLK_EMMC_SAMPLE:
rate = px30_mmc_get_clk(priv, clk->id);
break;
case SCLK_SFC:
rate = px30_sfc_get_clk(priv, clk->id);
break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2:
@ -1293,6 +1322,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_EMMC:
ret = px30_mmc_set_clk(priv, clk->id, rate);
break;
case SCLK_SFC:
ret = px30_sfc_set_clk(priv, clk->id, rate);
break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2:
@ -1651,7 +1683,7 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
struct px30_clk_priv *cru_priv;
struct px30_pmucru *pmucru = priv->pmucru;
u32 div;
ulong emmc_rate, sdmmc_rate, nandc_rate;
ulong emmc_rate, sdmmc_rate, nandc_rate, sfc_rate;
ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate;
ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate;
int ret;
@ -1685,8 +1717,9 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC);
sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC);
nandc_rate = px30_nandc_get_clk(cru_priv);
debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__,
emmc_rate, sdmmc_rate, nandc_rate);
sfc_rate = px30_sfc_get_clk(cru_priv, SCLK_SFC);
debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu sfc=%lu\n", __func__,
emmc_rate, sdmmc_rate, nandc_rate, sfc_rate);
/* avoid rate too large, reduce rate first */
px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div);
@ -1699,6 +1732,7 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div);
px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div);
px30_nandc_set_clk(cru_priv, nandc_rate / div);
px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate / div);
/* change gpll rate */
rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz);
@ -1716,6 +1750,7 @@ static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate);
px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate);
px30_nandc_set_clk(cru_priv, nandc_rate);
px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate);
return priv->gpll_hz;
}