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rv1126: ddr: rm phy soft reset code 

Change-Id: I60c9288da24304125de2951f45c28d5be33c5ce8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping 2020-07-23 20:13:44 +08:00 committed by Jianhong Chen
parent 8ecb6ff226
commit 95fd4f9d53
1 changed files with 0 additions and 12 deletions
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12
drivers/ram/rockchip/sdram_rv1126.c
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@ -346,16 +346,6 @@ static void rkclk_configure_ddr(struct dram_info *dram,
rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2);
}
static void phy_soft_reset(struct dram_info *dram)
{
void __iomem *phy_base = dram->phy;
clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
udelay(1);
setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET);
udelay(1);
}
static unsigned int
calculate_ddrconfig(struct rv1126_sdram_params *sdram_params)
{
@ -2272,8 +2262,6 @@ static u64 dram_detect_cap(struct dram_info *dram,
if (dram_type != LPDDR4) {
setbits_le32(PHY_REG(phy_base, 0xf), 0xf);
phy_soft_reset(dram);
if (data_training(dram, 0, sdram_params, 0,
READ_GATE_TRAINING) == 0)
cap_info->bw = 2;