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rockchip: dtsi: rk1808: sync from kernel 

base on commit 54e75c20:
    (clk: rockchip: rk1808: add clk ID for clk_rtc32k_frac)

Change-Id: Iac1db11af0e6c9d54e66a1d634d890ef6999c7d9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-10-11 10:25:05 +08:00 committed by Jianhong Chen
parent ba09f8360d
commit 8fd483da84
2 changed files with 12 additions and 11 deletions
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10
arch/arm/dts/rk1808.dtsi
View File

@ -1110,7 +1110,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff4c0000 0x0 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>;
clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
@ -1122,7 +1122,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff690000 0x0 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@ -1134,7 +1134,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff6a0000 0x0 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
@ -1146,7 +1146,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff6b0000 0x0 0x100>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
@ -1158,7 +1158,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff6c0000 0x0 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;

13
include/dt-bindings/clock/rk1808-cru.h
View File

@ -78,10 +78,10 @@
#define SCLK_SARADC 77
#define SCLK_EFUSE_S 78
#define SCLK_EFUSE_NS 79
#define SCLK_GPIO1 80
#define SCLK_GPIO2 81
#define SCLK_GPIO3 82
#define SCLK_GPIO4 83
#define DBCLK_GPIO1 80
#define DBCLK_GPIO2 81
#define DBCLK_GPIO3 82
#define DBCLK_GPIO4 83
#define SCLK_PWM0 84
#define SCLK_PWM1 85
#define SCLK_PWM2 86
@ -105,11 +105,12 @@
#define SCLK_UART0_PMU 104
#define SCLK_PVTM_PMU 105
#define SCLK_PMU_I2C0 106
#define SCLK_PMU_GPIO0 107
#define DBCLK_PMU_GPIO0 107
#define SCLK_REF24M_PMU 108
#define SCLK_USBPHY_REF 109
#define SCLK_MIPIDSIPHY_REF 110
#define SCLK_PCIEPHY_REF 111
#define SCLK_RTC32K_FRAC 112
/* aclk gates */
#define ACLK_GIC_PRE 145
@ -147,7 +148,6 @@
#define HCLK_VOPLITE 203
#define HCLK_RGA 204
#define HCLK_ISP 205
#define HCLK_CIF 205
#define LSCLK_PCIE 206
#define HCLK_HOST 207
#define LSCLK_PERI 208
@ -165,6 +165,7 @@
#define MSCLK_CORE_NIU 220
#define HSCLK_IMEM 221
#define HCLK_HOST_ARB 222
#define HCLK_CIF 223
/* pclk gates */
#define PCLK_DDR 250