clk: rockchip: rk3399: support clk dump
add clk_dump. add peri clk getting rate. modify aplll init freq to 816M. Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573 Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
Jianhong Chen
parent
cf04b7e8f2
commit
8b75ff3444
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@ -97,6 +97,7 @@ check_member(rk3399_cru, sdio1_con[1], 0x594);
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enum apll_frequencies {
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APLL_1600_MHZ,
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APLL_816_MHZ,
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APLL_600_MHZ,
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};
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@ -119,4 +120,10 @@ enum rk3399_pll_id {
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END_PLL_ID
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};
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struct rk3399_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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#endif /* __ASM_ARCH_CRU_RK3399_H_ */
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@ -56,13 +56,42 @@ static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1);
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static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1);
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static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
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static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
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static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
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static const struct pll_div *apll_cfgs[] = {
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[APLL_1600_MHZ] = &apll_1600_cfg,
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[APLL_816_MHZ] = &apll_816_cfg,
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[APLL_600_MHZ] = &apll_600_cfg,
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};
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#ifndef CONFIG_SPL_BUILD
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#define RK3399_CLK_DUMP(_id, _name, _iscru) \
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{ \
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.id = _id, \
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.name = _name, \
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.is_cru = _iscru, \
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}
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static const struct rk3399_clk_info clks_dump[] = {
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RK3399_CLK_DUMP(PLL_APLLL, "aplll", true),
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RK3399_CLK_DUMP(PLL_APLLB, "apllb", true),
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RK3399_CLK_DUMP(PLL_DPLL, "dpll", true),
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RK3399_CLK_DUMP(PLL_CPLL, "cpll", true),
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RK3399_CLK_DUMP(PLL_GPLL, "gpll", true),
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RK3399_CLK_DUMP(PLL_NPLL, "npll", true),
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RK3399_CLK_DUMP(PLL_VPLL, "vpll", true),
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RK3399_CLK_DUMP(ACLK_PERIHP, "aclk_perihp", true),
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RK3399_CLK_DUMP(HCLK_PERIHP, "hclk_perihp", true),
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RK3399_CLK_DUMP(PCLK_PERIHP, "pclk_perihp", true),
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RK3399_CLK_DUMP(ACLK_PERILP0, "aclk_perilp0", true),
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RK3399_CLK_DUMP(HCLK_PERILP0, "hclk_perilp0", true),
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RK3399_CLK_DUMP(PCLK_PERILP0, "pclk_perilp0", true),
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RK3399_CLK_DUMP(HCLK_PERILP1, "hclk_perilp1", true),
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RK3399_CLK_DUMP(PCLK_PERILP1, "pclk_perilp1", true),
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};
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#endif
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enum {
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/* PLL_CON0 */
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PLL_FBDIV_MASK = 0xfff,
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@ -1018,6 +1047,68 @@ static ulong rk3399_crypto_set_clk(struct rk3399_clk_priv *priv, ulong clk_id,
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return rk3399_crypto_get_clk(priv, clk_id);
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}
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static ulong rk3399_peri_get_clk(struct rk3399_clk_priv *priv, ulong clk_id)
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{
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struct rk3399_cru *cru = priv->cru;
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u32 div, con, parent;
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switch (clk_id) {
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case ACLK_PERIHP:
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con = readl(&cru->clksel_con[14]);
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div = (con & ACLK_PERIHP_DIV_CON_MASK) >>
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ACLK_PERIHP_DIV_CON_SHIFT;
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parent = GPLL_HZ;
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break;
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case PCLK_PERIHP:
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con = readl(&cru->clksel_con[14]);
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div = (con & PCLK_PERIHP_DIV_CON_MASK) >>
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PCLK_PERIHP_DIV_CON_SHIFT;
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parent = rk3399_peri_get_clk(priv, ACLK_PERIHP);
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break;
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case HCLK_PERIHP:
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con = readl(&cru->clksel_con[14]);
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div = (con & HCLK_PERIHP_DIV_CON_MASK) >>
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HCLK_PERIHP_DIV_CON_SHIFT;
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parent = rk3399_peri_get_clk(priv, ACLK_PERIHP);
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break;
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case ACLK_PERILP0:
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con = readl(&cru->clksel_con[23]);
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div = (con & ACLK_PERILP0_DIV_CON_MASK) >>
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ACLK_PERILP0_DIV_CON_SHIFT;
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parent = GPLL_HZ;
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break;
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case HCLK_PERILP0:
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con = readl(&cru->clksel_con[23]);
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div = (con & HCLK_PERILP0_DIV_CON_MASK) >>
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HCLK_PERILP0_DIV_CON_SHIFT;
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parent = rk3399_peri_get_clk(priv, ACLK_PERILP0);
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break;
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case PCLK_PERILP0:
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con = readl(&cru->clksel_con[23]);
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div = (con & PCLK_PERILP0_DIV_CON_MASK) >>
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PCLK_PERILP0_DIV_CON_SHIFT;
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parent = rk3399_peri_get_clk(priv, ACLK_PERILP0);
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break;
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case HCLK_PERILP1:
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con = readl(&cru->clksel_con[25]);
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div = (con & HCLK_PERILP1_DIV_CON_MASK) >>
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HCLK_PERILP1_DIV_CON_SHIFT;
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parent = GPLL_HZ;
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break;
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case PCLK_PERILP1:
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con = readl(&cru->clksel_con[25]);
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div = (con & PCLK_PERILP1_DIV_CON_MASK) >>
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PCLK_PERILP1_DIV_CON_SHIFT;
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parent = rk3399_peri_get_clk(priv, HCLK_PERILP1);
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break;
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default:
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return -ENOENT;
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}
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return DIV_TO_RATE(parent, div);
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}
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#endif
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static ulong rk3399_clk_get_rate(struct clk *clk)
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@ -1033,7 +1124,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
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case PLL_GPLL:
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case PLL_NPLL:
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case PLL_VPLL:
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rate = rk3399_pll_get_rate(priv, clk->id - 1);
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rate = rk3399_pll_get_rate(priv, clk->id);
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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@ -1075,6 +1166,16 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
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case SCLK_CRYPTO1:
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rate = rk3399_crypto_get_clk(priv, clk->id);
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break;
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case ACLK_PERIHP:
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case HCLK_PERIHP:
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case PCLK_PERIHP:
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case ACLK_PERILP0:
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case HCLK_PERILP0:
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case PCLK_PERILP0:
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case HCLK_PERILP1:
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case PCLK_PERILP1:
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rate = rk3399_peri_get_clk(priv, clk->id);
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break;
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#endif
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default:
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return -ENOENT;
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@ -1267,7 +1368,7 @@ static void rkclk_init(struct rk3399_cru *cru)
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u32 hclk_div;
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u32 pclk_div;
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rk3399_configure_cpu(cru, APLL_600_MHZ, CPU_CLUSTER_LITTLE);
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rk3399_configure_cpu(cru, APLL_816_MHZ, CPU_CLUSTER_LITTLE);
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/*
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* some cru registers changed by bootrom, we'd better reset them to
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@ -1621,3 +1722,71 @@ U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
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.platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
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#endif
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};
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#ifndef CONFIG_SPL_BUILD
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/**
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* soc_clk_dump() - Print clock frequencies
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* Returns zero on success
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*
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* Implementation for the clk dump command.
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*/
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int soc_clk_dump(void)
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{
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struct udevice *cru_dev, *pmucru_dev;
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const struct rk3399_clk_info *clk_dump;
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struct clk clk;
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unsigned long clk_count = ARRAY_SIZE(clks_dump);
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unsigned long rate;
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int i, ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(clk_rk3399),
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&cru_dev);
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if (ret) {
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printf("%s failed to get cru device\n", __func__);
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return ret;
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}
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(rockchip_rk3399_pmuclk),
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&pmucru_dev);
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if (ret) {
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printf("%s failed to get pmucru device\n", __func__);
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return ret;
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}
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printf("CLK:\n");
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for (i = 0; i < clk_count; i++) {
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clk_dump = &clks_dump[i];
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if (clk_dump->name) {
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clk.id = clk_dump->id;
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if (clk_dump->is_cru)
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ret = clk_request(cru_dev, &clk);
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else
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ret = clk_request(pmucru_dev, &clk);
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if (ret < 0)
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return ret;
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rate = clk_get_rate(&clk);
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clk_free(&clk);
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if (i == 0) {
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if (rate < 0)
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printf("%s %s\n", clk_dump->name,
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"unknown");
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else
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printf("%s %lu KHz\n", clk_dump->name,
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rate / 1000);
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} else {
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if (rate < 0)
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printf("%s %s\n", clk_dump->name,
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"unknown");
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else
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printf("%s %lu KHz\n", clk_dump->name,
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rate / 1000);
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}
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}
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}
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return 0;
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}
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#endif
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