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rockchip: px30: fix clk and pmugrf issue 

Change-Id: I481abacc5f69e645b4b3ca2cc5b27bf6cc3a6ca7
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This commit is contained in:
Joseph Chen 2018-02-06 10:43:16 +08:00
parent a60961a3df
commit 89f991f832
3 changed files with 7 additions and 3 deletions
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4
arch/arm/dts/px30-u-boot.dtsi
View File

@ -14,3 +14,7 @@
&emmc {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};

2
arch/arm/include/asm/arch-rockchip/cru_px30.h
View File

@ -12,7 +12,7 @@
#define OSC_HZ (24 * MHz)
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1200 * MHz)
#define GPLL_HZ (600 * MHz)
#define CPLL_HZ (594 * MHz)
#define CORE_PERI_HZ 204000000

2
drivers/ram/rockchip/sdram_px30.c
View File

@ -22,7 +22,7 @@ static int px30_dmc_probe(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(