From 89f991f8329ff91bbacc07baebeeafc014d57e94 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Tue, 6 Feb 2018 10:43:16 +0800 Subject: [PATCH] rockchip: px30: fix clk and pmugrf issue Change-Id: I481abacc5f69e645b4b3ca2cc5b27bf6cc3a6ca7 Signed-off-by: Joseph Chen --- arch/arm/dts/px30-u-boot.dtsi | 6 +++++- arch/arm/include/asm/arch-rockchip/cru_px30.h | 2 +- drivers/ram/rockchip/sdram_px30.c | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 1ece341901..83b7f11bb7 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -13,4 +13,8 @@ &emmc { u-boot,dm-pre-reloc; -}; \ No newline at end of file +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h index d27283f192..883cec0b79 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -12,7 +12,7 @@ #define OSC_HZ (24 * MHz) #define APLL_HZ (816 * MHz) -#define GPLL_HZ (1200 * MHz) +#define GPLL_HZ (600 * MHz) #define CPLL_HZ (594 * MHz) #define CORE_PERI_HZ 204000000 diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index a23e220571..f98ba8cc29 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -22,7 +22,7 @@ static int px30_dmc_probe(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); priv->info.base = CONFIG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size(