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video/drm: Rename rockchip-inno-mipi-dphy.c to inno_mipi_phy.c 

Change-Id: I20b9c24fc7df3f4fb74eb8ce7b722b945ac7d245
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi 2019-01-31 08:58:51 +08:00 committed by Kever Yang
parent a492b30692
commit 85e15df95e
3 changed files with 68 additions and 6 deletions
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7
drivers/video/drm/Kconfig
View File

@ -31,6 +31,13 @@ config ROCKCHIP_INNO_HDMI_PHY
use HDMI or TVE in RK322XH or RK322X, you should selet
this option.
config DRM_ROCKCHIP_INNO_MIPI_PHY
tristate "Rockchip INNO MIPI PHY driver"
depends on DRM_ROCKCHIP
help
Enable this to support the Rockchip MIPI PHY
with Innosilicon IP block.
config DRM_ROCKCHIP_INNO_VIDEO_PHY
tristate "Rockchip INNO LVDS/TTL PHY driver"
depends on DRM_ROCKCHIP

4
drivers/video/drm/Makefile
View File

@ -8,10 +8,10 @@ obj-y += rockchip_display.o rockchip_crtc.o rockchip_phy.o rockchip_bridge.o \
rockchip_vop.o rockchip_vop_reg.o bmp_helper.o
obj-$(CONFIG_DRM_ROCKCHIP_MIPI_DSI) += rockchip_mipi_dsi.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi.o \
rockchip-inno-mipi-dphy.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_HDMI) += rockchip_dw_hdmi.o dw_hdmi.o
obj-$(CONFIG_ROCKCHIP_INNO_HDMI_PHY) += rockchip-inno-hdmi-phy.o
obj-$(CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY) += inno_mipi_phy.o
obj-$(CONFIG_DRM_ROCKCHIP_INNO_VIDEO_PHY) += inno_video_phy.o
obj-$(CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY) += inno_video_combo_phy.o
obj-$(CONFIG_ROCKCHIP_DRM_TVE) += rockchip_drm_tve.o

63
drivers/video/drm/rockchip-inno-mipi-dphy.c → drivers/video/drm/inno_mipi_phy.c
View File

@ -17,11 +17,13 @@
#include <dm/uclass.h>
#include <dm/uclass-id.h>
#include "rockchip_display.h"
#include "rockchip_crtc.h"
#include "rockchip_connector.h"
#include "rockchip_phy.h"
#include "rockchip_mipi_dsi.h"
#define NSEC_PER_USEC 1000L
#define USEC_PER_SEC 1000000L
#define NSEC_PER_SEC 1000000000L
#define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l)))
/* Innosilicon MIPI D-PHY registers */
#define INNO_PHY_LANE_CTRL 0x00000
@ -115,6 +117,31 @@ enum lane_type {
DATA_LANE_3,
};
struct mipi_dphy_timing {
unsigned int clkmiss;
unsigned int clkpost;
unsigned int clkpre;
unsigned int clkprepare;
unsigned int clksettle;
unsigned int clktermen;
unsigned int clktrail;
unsigned int clkzero;
unsigned int dtermen;
unsigned int eot;
unsigned int hsexit;
unsigned int hsprepare;
unsigned int hszero;
unsigned int hssettle;
unsigned int hsskip;
unsigned int hstrail;
unsigned int init;
unsigned int lpx;
unsigned int taget;
unsigned int tago;
unsigned int tasure;
unsigned int wakeup;
};
struct inno_mipi_dphy_timing {
u8 lpx;
u8 hs_prepare;
@ -205,6 +232,34 @@ static inline void inno_update_bits(struct inno_mipi_dphy *inno, u32 reg,
inno_write(inno, reg, tmp);
}
static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
unsigned long period)
{
/* Global Operation Timing Parameters */
timing->clkmiss = 0;
timing->clkpost = 70 + 52 * period;
timing->clkpre = 8 * period;
timing->clkprepare = 65;
timing->clksettle = 95;
timing->clktermen = 0;
timing->clktrail = 80;
timing->clkzero = 260;
timing->dtermen = 0;
timing->eot = 0;
timing->hsexit = 120;
timing->hsprepare = 65 + 4 * period;
timing->hszero = 145 + 6 * period;
timing->hssettle = 85 + 6 * period;
timing->hsskip = 40;
timing->hstrail = max(8 * period, 60 + 4 * period);
timing->init = 100000;
timing->lpx = 60;
timing->taget = 5 * timing->lpx;
timing->tago = 4 * timing->lpx;
timing->tasure = 2 * timing->lpx;
timing->wakeup = 1000000;
}
static void inno_mipi_dphy_timing_update(struct inno_mipi_dphy *inno,
enum lane_type lane_type,
struct inno_mipi_dphy_timing *t)