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clk: rockchip: rv1126: Add PLL configuration for 1400MHz 

The rate of HPLL is 1400MHz.

Change-Id: I225017f7fb461124c74939828aee4a2a40222097
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2020-04-17 14:51:55 +08:00
parent 894a9e55a6
commit 85967b2028
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk_rv1126.c
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@ -40,6 +40,7 @@ static struct rockchip_cpu_rate_table rv1126_cpu_rates[] = {
static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),