x86: turn off cache: set control register properly

Bits should be ORed when they are supposed to be added together Signed-off-by: Ondrej Kupka <ondra.cap@gmail.com>
2011-09-30 21:05:11 +11:00 · 2011-09-30 21:05:11 +11:00 · 7b3d5380ee
parent ce5207e191
commit 7b3d5380ee
1 changed files with 1 additions and 1 deletions
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@ -50,7 +50,7 @@ board_init16_ret:

 	/* Turn of cache (this might require a 486-class CPU) */
 	movl	%cr0, %eax
-	orl	$(X86_CR0_NW & X86_CR0_CD), %eax
+	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
 	movl	%eax, %cr0
 	wbinvd