drm/rockchip: vop: add support px30
PX30 have two vop(vopb and vopl), the vopb have win0, win1 and win2, the vopl only have win1,most of register define is same with rk3366, so we porting the rk3366 vop register define for px30. win0: support yuv and scale; win1: support rgbx and afbdc format(vopb only); win2: support rgbx and four region; Change-Id: Ib9b796516e2bd43d98c79d5d3226a9e167739f76 Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
Kever Yang
parent
55e9fafcca
commit
7130fbf68d
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@ -22,6 +22,16 @@ static const struct rockchip_crtc rk3036_vop_data = {
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.data = &rk3036_vop,
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};
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static const struct rockchip_crtc px30_vop_lit_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &px30_vop_lit,
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};
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static const struct rockchip_crtc px30_vop_big_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &px30_vop_big,
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};
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static const struct rockchip_crtc rk3288_vop_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &rk3288_vop,
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@ -64,6 +74,12 @@ static const struct udevice_id rockchip_vop_ids[] = {
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}, {
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.compatible = "rockchip,rk3126-vop",
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.data = (ulong)&rk3036_vop_data,
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}, {
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.compatible = "rockchip,px30-vop-lit",
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.data = (ulong)&px30_vop_lit_data,
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}, {
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.compatible = "rockchip,px30-vop-big",
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.data = (ulong)&px30_vop_big_data,
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}, {
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.compatible = "rockchip,rk3288-vop",
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.data = (ulong)&rk3288_vop_data,
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@ -26,6 +26,8 @@ struct rockchip_crtc_funcs {
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struct vop_data;
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extern const struct rockchip_crtc_funcs rockchip_vop_funcs;
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extern const struct vop_data rk3036_vop;
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extern const struct vop_data px30_vop_lit;
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extern const struct vop_data px30_vop_big;
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extern const struct vop_data rk3288_vop;
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extern const struct vop_data rk3368_vop;
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extern const struct vop_data rk3366_vop;
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@ -239,17 +239,26 @@ struct vop_ctrl {
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struct vop_reg dclk_ddr;
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struct vop_reg p2i_en;
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struct vop_reg rgb_en;
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struct vop_reg lvds_en;
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struct vop_reg edp_en;
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struct vop_reg hdmi_en;
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struct vop_reg mipi_en;
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struct vop_reg data01_swap;
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struct vop_reg mipi_dual_channel_en;
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struct vop_reg dp_en;
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struct vop_reg dclk_pol;
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struct vop_reg pin_pol;
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struct vop_reg rgb_dclk_pol;
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struct vop_reg rgb_pin_pol;
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struct vop_reg lvds_dclk_pol;
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struct vop_reg lvds_pin_pol;
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struct vop_reg hdmi_dclk_pol;
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struct vop_reg hdmi_pin_pol;
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struct vop_reg edp_dclk_pol;
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struct vop_reg edp_pin_pol;
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struct vop_reg mipi_dclk_pol;
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struct vop_reg mipi_pin_pol;
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struct vop_reg dp_dclk_pol;
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struct vop_reg dp_pin_pol;
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struct vop_reg dither_up;
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@ -270,6 +279,49 @@ struct vop_ctrl {
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struct vop_reg ymirror;
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struct vop_reg dsp_background;
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/* CABC */
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struct vop_reg cabc_total_num;
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struct vop_reg cabc_config_mode;
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struct vop_reg cabc_stage_up_mode;
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struct vop_reg cabc_scale_cfg_value;
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struct vop_reg cabc_scale_cfg_enable;
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struct vop_reg cabc_global_dn_limit_en;
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struct vop_reg cabc_lut_en;
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struct vop_reg cabc_en;
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struct vop_reg cabc_handle_en;
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struct vop_reg cabc_stage_up;
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struct vop_reg cabc_stage_down;
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struct vop_reg cabc_global_dn;
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struct vop_reg cabc_calc_pixel_num;
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/* BCSH */
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struct vop_reg bcsh_brightness;
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struct vop_reg bcsh_contrast;
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struct vop_reg bcsh_sat_con;
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struct vop_reg bcsh_sin_hue;
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struct vop_reg bcsh_cos_hue;
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struct vop_reg bcsh_r2y_csc_mode;
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struct vop_reg bcsh_r2y_en;
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struct vop_reg bcsh_y2r_csc_mode;
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struct vop_reg bcsh_y2r_en;
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struct vop_reg bcsh_color_bar;
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struct vop_reg bcsh_out_mode;
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struct vop_reg bcsh_en;
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/* MCU OUTPUT */
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struct vop_reg mcu_pix_total;
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struct vop_reg mcu_cs_pst;
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struct vop_reg mcu_cs_pend;
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struct vop_reg mcu_rw_pst;
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struct vop_reg mcu_rw_pend;
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struct vop_reg mcu_clk_sel;
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struct vop_reg mcu_hold_mode;
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struct vop_reg mcu_frame_st;
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struct vop_reg mcu_rs;
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struct vop_reg mcu_bypass;
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struct vop_reg mcu_type;
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struct vop_reg mcu_rw_bypass_port;
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struct vop_reg win_gate[4];
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struct vop_reg cfg_done;
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};
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@ -315,3 +315,126 @@ const struct vop_data rk3036_vop = {
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.line_flag = &rk3036_vop_line_flag,
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.reg_len = RK3036_DSP_VACT_ST_END_F1 * 4,
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};
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static const struct vop_scl_regs rk3366_lit_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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.scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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.scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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};
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static const struct vop_win rk3366_win0_data = {
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.scl = &rk3366_lit_win_scl,
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.enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
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.rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
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.act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
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.dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
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.dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
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.yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
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.uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
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.alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
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.alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
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};
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static const struct vop_win rk3366_win1_data = {
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.enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
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.format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
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.rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
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.dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
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.dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
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.yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
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.alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
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.alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
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};
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static const struct vop_ctrl px30_ctrl_data = {
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.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
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.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
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.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
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.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
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.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
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.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
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.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
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.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
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.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
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.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
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.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22),
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.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
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.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
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.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
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.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
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.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
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.hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
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.hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
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.lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
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.lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
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.mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
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.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
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.mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
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.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
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.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
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.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
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.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
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.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
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.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
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.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
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.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
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.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
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.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
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.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
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.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
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.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
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.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
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.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
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.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
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.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
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.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
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.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
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.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
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.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
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.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
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.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
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.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
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.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
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.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
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.cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2),
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.cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4),
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.cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1),
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.cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0),
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.cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4),
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.cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0),
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.cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19),
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.cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8),
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.cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0),
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.cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0),
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.cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8),
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};
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static const struct vop_line_flag rk3366_vop_lite_line_flag = {
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.line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
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};
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const struct vop_data px30_vop_lit = {
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.version = VOP_VERSION(2, 5),
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.ctrl = &px30_ctrl_data,
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.win = &rk3366_win1_data,
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.line_flag = &rk3366_vop_lite_line_flag,
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.reg_len = RK3366_LIT_FRC_LOWER01_0 * 4,
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};
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const struct vop_data px30_vop_big = {
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.version = VOP_VERSION(2, 6),
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.ctrl = &px30_ctrl_data,
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.win = &rk3366_win0_data,
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.line_flag = &rk3366_vop_lite_line_flag,
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.reg_len = RK3366_LIT_FRC_LOWER01_0 * 4,
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};
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@ -869,4 +869,87 @@
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#define RK3036_HWC_LUT_ADDR 0x800
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/* rk3036 register definition end */
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/* rk3366 register definition */
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#define RK3366_LIT_REG_CFG_DONE 0x00000
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#define RK3366_LIT_VERSION 0x00004
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#define RK3366_LIT_DSP_BG 0x00008
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#define RK3366_LIT_MCU_CTRL 0x0000c
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#define RK3366_LIT_SYS_CTRL0 0x00010
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#define RK3366_LIT_SYS_CTRL1 0x00014
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#define RK3366_LIT_SYS_CTRL2 0x00018
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#define RK3366_LIT_DSP_CTRL0 0x00020
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#define RK3366_LIT_DSP_CTRL2 0x00028
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#define RK3366_LIT_VOP_STATUS 0x0002c
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#define RK3366_LIT_LINE_FLAG 0x00030
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#define RK3366_LIT_INTR_EN 0x00034
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#define RK3366_LIT_INTR_CLEAR 0x00038
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#define RK3366_LIT_INTR_STATUS 0x0003c
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#define RK3366_LIT_WIN0_CTRL0 0x00050
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#define RK3366_LIT_WIN0_CTRL1 0x00054
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#define RK3366_LIT_WIN0_COLOR_KEY 0x00058
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#define RK3366_LIT_WIN0_VIR 0x0005c
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#define RK3366_LIT_WIN0_YRGB_MST0 0x00060
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#define RK3366_LIT_WIN0_CBR_MST0 0x00064
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#define RK3366_LIT_WIN0_ACT_INFO 0x00068
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#define RK3366_LIT_WIN0_DSP_INFO 0x0006c
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#define RK3366_LIT_WIN0_DSP_ST 0x00070
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#define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074
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#define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078
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#define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c
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#define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080
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#define RK3366_LIT_WIN1_CTRL0 0x00090
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#define RK3366_LIT_WIN1_CTRL1 0x00094
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#define RK3366_LIT_WIN1_VIR 0x00098
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#define RK3366_LIT_WIN1_MST 0x000a0
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#define RK3366_LIT_WIN1_DSP_INFO 0x000a4
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#define RK3366_LIT_WIN1_DSP_ST 0x000a8
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#define RK3366_LIT_WIN1_COLOR_KEY 0x000ac
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#define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc
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#define RK3366_LIT_HWC_CTRL0 0x000e0
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#define RK3366_LIT_HWC_CTRL1 0x000e4
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#define RK3366_LIT_HWC_MST 0x000e8
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#define RK3366_LIT_HWC_DSP_ST 0x000ec
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#define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0
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#define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100
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#define RK3366_LIT_DSP_HACT_ST_END 0x00104
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#define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108
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#define RK3366_LIT_DSP_VACT_ST_END 0x0010c
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||||
#define RK3366_LIT_DSP_VS_ST_END_F1 0x00110
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#define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114
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#define RK3366_LIT_BCSH_CTRL 0x00160
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#define RK3366_LIT_BCSH_COL_BAR 0x00164
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#define RK3366_LIT_BCSH_BCS 0x00168
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#define RK3366_LIT_BCSH_H 0x0016c
|
||||
#define RK3366_LIT_FRC_LOWER01_0 0x00170
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#define RK3366_LIT_FRC_LOWER01_1 0x00174
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||||
#define RK3366_LIT_FRC_LOWER10_0 0x00178
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||||
#define RK3366_LIT_FRC_LOWER10_1 0x0017c
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#define RK3366_LIT_FRC_LOWER11_0 0x00180
|
||||
#define RK3366_LIT_FRC_LOWER11_1 0x00184
|
||||
#define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c
|
||||
#define RK3366_LIT_DBG_REG_000 0x00190
|
||||
#define RK3366_LIT_BLANKING_VALUE 0x001f4
|
||||
#define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8
|
||||
#define RK3366_LIT_FLAG_REG 0x001fc
|
||||
#define RK3366_LIT_HWC_LUT_ADDR 0x00600
|
||||
#define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00
|
||||
/* rk3366 register definition end */
|
||||
|
||||
/* px30 register definition */
|
||||
#define PX30_CABC_CTRL0 0x00200
|
||||
#define PX30_CABC_CTRL1 0x00204
|
||||
#define PX30_CABC_CTRL2 0x00208
|
||||
#define PX30_CABC_CTRL3 0x0020c
|
||||
#define PX30_CABC_GAUSS_LINE0_0 0x00210
|
||||
#define PX30_CABC_GAUSS_LINE0_1 0x00214
|
||||
#define PX30_CABC_GAUSS_LINE1_0 0x00218
|
||||
#define PX30_CABC_GAUSS_LINE1_1 0x0021c
|
||||
#define PX30_CABC_GAUSS_LINE2_0 0x00220
|
||||
#define PX30_CABC_GAUSS_LINE2_1 0x00224
|
||||
#define PX30_AFBCD0_CTRL 0x00240
|
||||
#define PX30_AFBCD0_HDR_PTR 0x00244
|
||||
#define PX30_AFBCD0_PIC_SIZE 0x00248
|
||||
#define PX30_AFBCD0_PIC_OFFSET 0x0024c
|
||||
#define PX30_AFBCD0_AXI_CTRL 0x00250
|
||||
/* px30 register definition end */
|
||||
#endif /* _ROCKCHIP_VOP_REG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue