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rv1126: ddr: update drv odt table 

Change-Id: Ic20957d02c36fe2d167c1a63b5e016535a181baf
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping 2020-07-23 19:46:09 +08:00 committed by Jianhong Chen
parent d5bb9a92b1
commit 70fee8b333
3 changed files with 265 additions and 267 deletions
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278
arch/arm/include/asm/arch-rockchip/sdram_rv1126.h
View File

@ -19,158 +19,156 @@
#define AGING_OTHER_VAL (0x33)
#define PATTERN (0x5aa5f00f)
#define PHY_PER_DE_SKEW_DELAY (20)
#define PHY_RX_DQS_INNER_DELAY (5)
#define PHY_DDR3_RON_DISABLE (0)
#define PHY_DDR3_RON_506ohm (1)
#define PHY_DDR3_RON_253ohm (2)
#define PHY_DDR3_RON_169hm (3)
#define PHY_DDR3_RON_127ohm (4)
#define PHY_DDR3_RON_101ohm (5)
#define PHY_DDR3_RON_84ohm (6)
#define PHY_DDR3_RON_72ohm (7)
#define PHY_DDR3_RON_63ohm (16)
#define PHY_DDR3_RON_56ohm (17)
#define PHY_DDR3_RON_51ohm (18)
#define PHY_DDR3_RON_46ohm (19)
#define PHY_DDR3_RON_42ohm (20)
#define PHY_DDR3_RON_39ohm (21)
#define PHY_DDR3_RON_36ohm (22)
#define PHY_DDR3_RON_34ohm (23)
#define PHY_DDR3_RON_32ohm (24)
#define PHY_DDR3_RON_30ohm (25)
#define PHY_DDR3_RON_28ohm (26)
#define PHY_DDR3_RON_27ohm (27)
#define PHY_DDR3_RON_25ohm (28)
#define PHY_DDR3_RON_24ohm (29)
#define PHY_DDR3_RON_23ohm (30)
#define PHY_DDR3_RON_22ohm (31)
#define PHY_DDR3_RON_455ohm (1)
#define PHY_DDR3_RON_230ohm (2)
#define PHY_DDR3_RON_153ohm (3)
#define PHY_DDR3_RON_115ohm (4)
#define PHY_DDR3_RON_91ohm (5)
#define PHY_DDR3_RON_76ohm (6)
#define PHY_DDR3_RON_65ohm (7)
#define PHY_DDR3_RON_57ohm (16)
#define PHY_DDR3_RON_51ohm (17)
#define PHY_DDR3_RON_46ohm (18)
#define PHY_DDR3_RON_41ohm (19)
#define PHY_DDR3_RON_38ohm (20)
#define PHY_DDR3_RON_35ohm (21)
#define PHY_DDR3_RON_32ohm (22)
#define PHY_DDR3_RON_30ohm (23)
#define PHY_DDR3_RON_28ohm (24)
#define PHY_DDR3_RON_27ohm (25)
#define PHY_DDR3_RON_25ohm (26)
#define PHY_DDR3_RON_24ohm (27)
#define PHY_DDR3_RON_23ohm (28)
#define PHY_DDR3_RON_22ohm (29)
#define PHY_DDR3_RON_21ohm (30)
#define PHY_DDR3_RON_20ohm (31)
#define PHY_DDR3_RTT_DISABLE (0)
#define PHY_DDR3_RTT_953ohm (1)
#define PHY_DDR3_RTT_483ohm (2)
#define PHY_DDR3_RTT_320ohm (3)
#define PHY_DDR3_RTT_241ohm (4)
#define PHY_DDR3_RTT_193ohm (5)
#define PHY_DDR3_RTT_161ohm (6)
#define PHY_DDR3_RTT_138ohm (7)
#define PHY_DDR3_RTT_121ohm (16)
#define PHY_DDR3_RTT_107ohm (17)
#define PHY_DDR3_RTT_97ohm (18)
#define PHY_DDR3_RTT_88ohm (19)
#define PHY_DDR3_RTT_80ohm (20)
#define PHY_DDR3_RTT_74ohm (21)
#define PHY_DDR3_RTT_69ohm (22)
#define PHY_DDR3_RTT_64ohm (23)
#define PHY_DDR3_RTT_60ohm (24)
#define PHY_DDR3_RTT_57ohm (25)
#define PHY_DDR3_RTT_54ohm (26)
#define PHY_DDR3_RTT_51ohm (27)
#define PHY_DDR3_RTT_48ohm (28)
#define PHY_DDR3_RTT_46ohm (29)
#define PHY_DDR3_RTT_44ohm (30)
#define PHY_DDR3_RTT_42ohm (31)
#define PHY_DDR3_RTT_561ohm (1)
#define PHY_DDR3_RTT_282ohm (2)
#define PHY_DDR3_RTT_188ohm (3)
#define PHY_DDR3_RTT_141ohm (4)
#define PHY_DDR3_RTT_113ohm (5)
#define PHY_DDR3_RTT_94ohm (6)
#define PHY_DDR3_RTT_81ohm (7)
#define PHY_DDR3_RTT_72ohm (16)
#define PHY_DDR3_RTT_64ohm (17)
#define PHY_DDR3_RTT_58ohm (18)
#define PHY_DDR3_RTT_52ohm (19)
#define PHY_DDR3_RTT_48ohm (20)
#define PHY_DDR3_RTT_44ohm (21)
#define PHY_DDR3_RTT_41ohm (22)
#define PHY_DDR3_RTT_38ohm (23)
#define PHY_DDR3_RTT_37ohm (24)
#define PHY_DDR3_RTT_34ohm (25)
#define PHY_DDR3_RTT_32ohm (26)
#define PHY_DDR3_RTT_31ohm (27)
#define PHY_DDR3_RTT_29ohm (28)
#define PHY_DDR3_RTT_28ohm (29)
#define PHY_DDR3_RTT_27ohm (30)
#define PHY_DDR3_RTT_25ohm (31)
#define PHY_DDR4_LPDDR3_RON_DISABLE (0)
#define PHY_DDR4_LPDDR3_RON_570ohm (1)
#define PHY_DDR4_LPDDR3_RON_285ohm (2)
#define PHY_DDR4_LPDDR3_RON_190ohm (3)
#define PHY_DDR4_LPDDR3_RON_142ohm (4)
#define PHY_DDR4_LPDDR3_RON_114ohm (5)
#define PHY_DDR4_LPDDR3_RON_95ohm (6)
#define PHY_DDR4_LPDDR3_RON_81ohm (7)
#define PHY_DDR4_LPDDR3_RON_71ohm (16)
#define PHY_DDR4_LPDDR3_RON_63ohm (17)
#define PHY_DDR4_LPDDR3_RON_57ohm (18)
#define PHY_DDR4_LPDDR3_RON_52ohm (19)
#define PHY_DDR4_LPDDR3_RON_47ohm (20)
#define PHY_DDR4_LPDDR3_RON_44ohm (21)
#define PHY_DDR4_LPDDR3_RON_41ohm (22)
#define PHY_DDR4_LPDDR3_RON_38ohm (23)
#define PHY_DDR4_LPDDR3_RON_36ohm (24)
#define PHY_DDR4_LPDDR3_RON_34ohm (25)
#define PHY_DDR4_LPDDR3_RON_32ohm (26)
#define PHY_DDR4_LPDDR3_RON_30ohm (27)
#define PHY_DDR4_LPDDR3_RON_28ohm (28)
#define PHY_DDR4_LPDDR3_RON_27ohm (29)
#define PHY_DDR4_LPDDR3_RON_26ohm (30)
#define PHY_DDR4_LPDDR3_RON_25ohm (31)
#define PHY_DDR4_LPDDR3_RON_482ohm (1)
#define PHY_DDR4_LPDDR3_RON_244ohm (2)
#define PHY_DDR4_LPDDR3_RON_162ohm (3)
#define PHY_DDR4_LPDDR3_RON_122ohm (4)
#define PHY_DDR4_LPDDR3_RON_97ohm (5)
#define PHY_DDR4_LPDDR3_RON_81ohm (6)
#define PHY_DDR4_LPDDR3_RON_69ohm (7)
#define PHY_DDR4_LPDDR3_RON_61ohm (16)
#define PHY_DDR4_LPDDR3_RON_54ohm (17)
#define PHY_DDR4_LPDDR3_RON_48ohm (18)
#define PHY_DDR4_LPDDR3_RON_44ohm (19)
#define PHY_DDR4_LPDDR3_RON_40ohm (20)
#define PHY_DDR4_LPDDR3_RON_37ohm (21)
#define PHY_DDR4_LPDDR3_RON_34ohm (22)
#define PHY_DDR4_LPDDR3_RON_32ohm (23)
#define PHY_DDR4_LPDDR3_RON_30ohm (24)
#define PHY_DDR4_LPDDR3_RON_28ohm (25)
#define PHY_DDR4_LPDDR3_RON_27ohm (26)
#define PHY_DDR4_LPDDR3_RON_25ohm (27)
#define PHY_DDR4_LPDDR3_RON_24ohm (28)
#define PHY_DDR4_LPDDR3_RON_23ohm (29)
#define PHY_DDR4_LPDDR3_RON_22ohm (30)
#define PHY_DDR4_LPDDR3_RON_21ohm (31)
#define PHY_DDR4_LPDDR3_RTT_DISABLE (0)
#define PHY_DDR4_LPDDR3_RTT_973ohm (1)
#define PHY_DDR4_LPDDR3_RTT_493ohm (2)
#define PHY_DDR4_LPDDR3_RTT_327ohm (3)
#define PHY_DDR4_LPDDR3_RTT_247ohm (4)
#define PHY_DDR4_LPDDR3_RTT_197ohm (5)
#define PHY_DDR4_LPDDR3_RTT_164ohm (6)
#define PHY_DDR4_LPDDR3_RTT_141ohm (7)
#define PHY_DDR4_LPDDR3_RTT_123ohm (16)
#define PHY_DDR4_LPDDR3_RTT_109ohm (17)
#define PHY_DDR4_LPDDR3_RTT_99ohm (18)
#define PHY_DDR4_LPDDR3_RTT_90ohm (19)
#define PHY_DDR4_LPDDR3_RTT_82ohm (20)
#define PHY_DDR4_LPDDR3_RTT_76ohm (21)
#define PHY_DDR4_LPDDR3_RTT_70ohm (22)
#define PHY_DDR4_LPDDR3_RTT_66ohm (23)
#define PHY_DDR4_LPDDR3_RTT_62ohm (24)
#define PHY_DDR4_LPDDR3_RTT_58ohm (25)
#define PHY_DDR4_LPDDR3_RTT_55ohm (26)
#define PHY_DDR4_LPDDR3_RTT_52ohm (27)
#define PHY_DDR4_LPDDR3_RTT_49ohm (28)
#define PHY_DDR4_LPDDR3_RTT_47ohm (29)
#define PHY_DDR4_LPDDR3_RTT_45ohm (30)
#define PHY_DDR4_LPDDR3_RTT_43ohm (31)
#define PHY_DDR4_LPDDR3_RTT_586ohm (1)
#define PHY_DDR4_LPDDR3_RTT_294ohm (2)
#define PHY_DDR4_LPDDR3_RTT_196ohm (3)
#define PHY_DDR4_LPDDR3_RTT_148ohm (4)
#define PHY_DDR4_LPDDR3_RTT_118ohm (5)
#define PHY_DDR4_LPDDR3_RTT_99ohm (6)
#define PHY_DDR4_LPDDR3_RTT_85ohm (7)
#define PHY_DDR4_LPDDR3_RTT_76ohm (16)
#define PHY_DDR4_LPDDR3_RTT_67ohm (17)
#define PHY_DDR4_LPDDR3_RTT_60ohm (18)
#define PHY_DDR4_LPDDR3_RTT_55ohm (19)
#define PHY_DDR4_LPDDR3_RTT_50ohm (20)
#define PHY_DDR4_LPDDR3_RTT_46ohm (21)
#define PHY_DDR4_LPDDR3_RTT_43ohm (22)
#define PHY_DDR4_LPDDR3_RTT_40ohm (23)
#define PHY_DDR4_LPDDR3_RTT_38ohm (24)
#define PHY_DDR4_LPDDR3_RTT_36ohm (25)
#define PHY_DDR4_LPDDR3_RTT_34ohm (26)
#define PHY_DDR4_LPDDR3_RTT_32ohm (27)
#define PHY_DDR4_LPDDR3_RTT_31ohm (28)
#define PHY_DDR4_LPDDR3_RTT_29ohm (29)
#define PHY_DDR4_LPDDR3_RTT_28ohm (30)
#define PHY_DDR4_LPDDR3_RTT_27ohm (31)
#define PHY_LPDDR4_RON_DISABLE (0)
#define PHY_LPDDR4_RON_606ohm (1)
#define PHY_LPDDR4_RON_303ohm (2)
#define PHY_LPDDR4_RON_202ohm (3)
#define PHY_LPDDR4_RON_152ohm (4)
#define PHY_LPDDR4_RON_121ohm (5)
#define PHY_LPDDR4_RON_101ohm (6)
#define PHY_LPDDR4_RON_87ohm (7)
#define PHY_LPDDR4_RON_76ohm (16)
#define PHY_LPDDR4_RON_67ohm (17)
#define PHY_LPDDR4_RON_61ohm (18)
#define PHY_LPDDR4_RON_55ohm (19)
#define PHY_LPDDR4_RON_51ohm (20)
#define PHY_LPDDR4_RON_47ohm (21)
#define PHY_LPDDR4_RON_43ohm (22)
#define PHY_LPDDR4_RON_40ohm (23)
#define PHY_LPDDR4_RON_38ohm (24)
#define PHY_LPDDR4_RON_36ohm (25)
#define PHY_LPDDR4_RON_34ohm (26)
#define PHY_LPDDR4_RON_32ohm (27)
#define PHY_LPDDR4_RON_30ohm (28)
#define PHY_LPDDR4_RON_29ohm (29)
#define PHY_LPDDR4_RON_28ohm (30)
#define PHY_LPDDR4_RON_26ohm (31)
#define PHY_LPDDR4_RON_501ohm (1)
#define PHY_LPDDR4_RON_253ohm (2)
#define PHY_LPDDR4_RON_168ohm (3)
#define PHY_LPDDR4_RON_126ohm (4)
#define PHY_LPDDR4_RON_101ohm (5)
#define PHY_LPDDR4_RON_84ohm (6)
#define PHY_LPDDR4_RON_72ohm (7)
#define PHY_LPDDR4_RON_63ohm (16)
#define PHY_LPDDR4_RON_56ohm (17)
#define PHY_LPDDR4_RON_50ohm (18)
#define PHY_LPDDR4_RON_46ohm (19)
#define PHY_LPDDR4_RON_42ohm (20)
#define PHY_LPDDR4_RON_38ohm (21)
#define PHY_LPDDR4_RON_36ohm (22)
#define PHY_LPDDR4_RON_33ohm (23)
#define PHY_LPDDR4_RON_31ohm (24)
#define PHY_LPDDR4_RON_29ohm (25)
#define PHY_LPDDR4_RON_28ohm (26)
#define PHY_LPDDR4_RON_26ohm (27)
#define PHY_LPDDR4_RON_25ohm (28)
#define PHY_LPDDR4_RON_24ohm (29)
#define PHY_LPDDR4_RON_23ohm (30)
#define PHY_LPDDR4_RON_22ohm (31)
#define PHY_LPDDR4_RTT_DISABLE (0)
#define PHY_LPDDR4_RTT_998ohm (1)
#define PHY_LPDDR4_RTT_506ohm (2)
#define PHY_LPDDR4_RTT_336ohm (3)
#define PHY_LPDDR4_RTT_253ohm (4)
#define PHY_LPDDR4_RTT_202ohm (5)
#define PHY_LPDDR4_RTT_169ohm (6)
#define PHY_LPDDR4_RTT_144ohm (7)
#define PHY_LPDDR4_RTT_127ohm (16)
#define PHY_LPDDR4_RTT_112ohm (17)
#define PHY_LPDDR4_RTT_101ohm (18)
#define PHY_LPDDR4_RTT_92ohm (19)
#define PHY_LPDDR4_RTT_84ohm (20)
#define PHY_LPDDR4_RTT_78ohm (21)
#define PHY_LPDDR4_RTT_72ohm (22)
#define PHY_LPDDR4_RTT_67ohm (23)
#define PHY_LPDDR4_RTT_63ohm (24)
#define PHY_LPDDR4_RTT_60ohm (25)
#define PHY_LPDDR4_RTT_56ohm (26)
#define PHY_LPDDR4_RTT_53ohm (27)
#define PHY_LPDDR4_RTT_51ohm (28)
#define PHY_LPDDR4_RTT_48ohm (29)
#define PHY_LPDDR4_RTT_46ohm (30)
#define PHY_LPDDR4_RTT_44ohm (31)
#define PHY_LPDDR4_RTT_604ohm (1)
#define PHY_LPDDR4_RTT_303ohm (2)
#define PHY_LPDDR4_RTT_202ohm (3)
#define PHY_LPDDR4_RTT_152ohm (4)
#define PHY_LPDDR4_RTT_122ohm (5)
#define PHY_LPDDR4_RTT_101ohm (6)
#define PHY_LPDDR4_RTT_87ohm (7)
#define PHY_LPDDR4_RTT_78ohm (16)
#define PHY_LPDDR4_RTT_69ohm (17)
#define PHY_LPDDR4_RTT_62ohm (18)
#define PHY_LPDDR4_RTT_56ohm (19)
#define PHY_LPDDR4_RTT_52ohm (20)
#define PHY_LPDDR4_RTT_48ohm (21)
#define PHY_LPDDR4_RTT_44ohm (22)
#define PHY_LPDDR4_RTT_41ohm (23)
#define PHY_LPDDR4_RTT_39ohm (24)
#define PHY_LPDDR4_RTT_37ohm (25)
#define PHY_LPDDR4_RTT_35ohm (26)
#define PHY_LPDDR4_RTT_33ohm (27)
#define PHY_LPDDR4_RTT_32ohm (28)
#define PHY_LPDDR4_RTT_30ohm (29)
#define PHY_LPDDR4_RTT_29ohm (30)
#define PHY_LPDDR4_RTT_27ohm (31)
#define ADD_CMD_CA (0x150)
#define ADD_GROUP_CS0_A (0x170)

40
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-loader_params.inc
View File

@ -18,13 +18,13 @@
(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
/* drv when odt on */
(34 << PHY_DQ_DRV_SHIFT) | (34 << PHY_CA_DRV_SHIFT) |
(42 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
(30 << PHY_DQ_DRV_SHIFT) | (30 << PHY_CA_DRV_SHIFT) |
(38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
/* drv when odt off */
(34 << PHY_DQ_DRV_SHIFT) | (34 << PHY_CA_DRV_SHIFT) |
(42 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
(30 << PHY_DQ_DRV_SHIFT) | (30 << PHY_CA_DRV_SHIFT) |
(38 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
/* odt info */
(120 << DRAM_ODT_SHIFT) | (241 << PHY_ODT_SHIFT) |
(120 << DRAM_ODT_SHIFT) | (141 << PHY_ODT_SHIFT) |
(1 << PHY_ODT_PUUP_EN_SHIFT) |
(1 << PHY_ODT_PUDN_EN_SHIFT),
/* odt enable freq */
@ -41,13 +41,13 @@
(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
/* drv when odt on */
(34 << PHY_DQ_DRV_SHIFT) | (34 << PHY_CA_DRV_SHIFT) |
(42 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
(28 << PHY_DQ_DRV_SHIFT) | (28 << PHY_CA_DRV_SHIFT) |
(37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
/* drv when odt off */
(34 << PHY_DQ_DRV_SHIFT) | (42 << PHY_CA_DRV_SHIFT) |
(42 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
(28 << PHY_DQ_DRV_SHIFT) | (28 << PHY_CA_DRV_SHIFT) |
(37 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
/* odt info */
(120 << DRAM_ODT_SHIFT) | (247 << PHY_ODT_SHIFT) |
(120 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) |
(1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT),
/* odt enable freq */
(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT),
@ -63,13 +63,13 @@
(528 << DDR_FREQ_F2_SHIFT) | (784 << DDR_FREQ_F3_SHIFT),
(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
/* drv when odt on */
(34 << PHY_DQ_DRV_SHIFT) | (44 << PHY_CA_DRV_SHIFT) |
(41 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) |
(34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
/* drv when odt off */
(49 << PHY_DQ_DRV_SHIFT) | (54 << PHY_CA_DRV_SHIFT) |
(44 << PHY_CLK_DRV_SHIFT) | (48 << DRAM_DQ_DRV_SHIFT),
(28 << PHY_DQ_DRV_SHIFT) | (37 << PHY_CA_DRV_SHIFT) |
(34 << PHY_CLK_DRV_SHIFT) | (34 << DRAM_DQ_DRV_SHIFT),
/* odt info */
(240 << DRAM_ODT_SHIFT) | (247 << PHY_ODT_SHIFT) |
(240 << DRAM_ODT_SHIFT) | (148 << PHY_ODT_SHIFT) |
(1 << PHY_ODT_PUUP_EN_SHIFT) | (1 << PHY_ODT_PUDN_EN_SHIFT),
/* odt enable freq */
(333 << DRAM_ODT_EN_FREQ_SHIFT) | (333 << PHY_ODT_EN_FREQ_SHIFT),
@ -87,14 +87,14 @@
(0 << DDR_FREQ_F4_SHIFT) | (0 << DDR_FREQ_F5_SHIFT),
/* drv when odt on */
(40 << PHY_DQ_DRV_SHIFT) | (40 << PHY_CA_DRV_SHIFT) |
(40 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT),
(33 << PHY_DQ_DRV_SHIFT) | (33 << PHY_CA_DRV_SHIFT) |
(33 << PHY_CLK_DRV_SHIFT) | (40 << DRAM_DQ_DRV_SHIFT),
/* drv when odt off */
(40 << PHY_DQ_DRV_SHIFT) |
(40 << PHY_CA_DRV_SHIFT) | (40 << PHY_CLK_DRV_SHIFT) |
(33 << PHY_DQ_DRV_SHIFT) |
(33 << PHY_CA_DRV_SHIFT) | (33 << PHY_CLK_DRV_SHIFT) |
(80 << DRAM_DQ_DRV_SHIFT),
/* odt info and PU-cal info */
(240 << DRAM_ODT_SHIFT) | (120 << PHY_ODT_SHIFT) |
(240 << DRAM_ODT_SHIFT) | (78 << PHY_ODT_SHIFT) |
(0 << LP4_CA_ODT_SHIFT) |
(LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTEN_SHIFT) |
(LPDDR4_VDDQ_2_5 << LP4_DRV_PU_CAL_ODTOFF_SHIFT) |

214
drivers/ram/rockchip/sdram_rv1126.c
View File

@ -553,21 +553,19 @@ static void phy_pll_set(struct dram_info *dram, u32 freq, u32 wait)
}
static const u16 d3_phy_drv_2_ohm[][2] = {
{PHY_DDR3_RON_506ohm, 506},
{PHY_DDR3_RON_253ohm, 253},
{PHY_DDR3_RON_169hm, 169},
{PHY_DDR3_RON_127ohm, 127},
{PHY_DDR3_RON_101ohm, 101},
{PHY_DDR3_RON_84ohm, 84},
{PHY_DDR3_RON_72ohm, 72},
{PHY_DDR3_RON_63ohm, 63},
{PHY_DDR3_RON_56ohm, 56},
{PHY_DDR3_RON_455ohm, 455},
{PHY_DDR3_RON_230ohm, 230},
{PHY_DDR3_RON_153ohm, 153},
{PHY_DDR3_RON_115ohm, 115},
{PHY_DDR3_RON_91ohm, 91},
{PHY_DDR3_RON_76ohm, 76},
{PHY_DDR3_RON_65ohm, 65},
{PHY_DDR3_RON_57ohm, 57},
{PHY_DDR3_RON_51ohm, 51},
{PHY_DDR3_RON_46ohm, 46},
{PHY_DDR3_RON_42ohm, 42},
{PHY_DDR3_RON_39ohm, 39},
{PHY_DDR3_RON_36ohm, 36},
{PHY_DDR3_RON_34ohm, 34},
{PHY_DDR3_RON_41ohm, 41},
{PHY_DDR3_RON_38ohm, 38},
{PHY_DDR3_RON_35ohm, 35},
{PHY_DDR3_RON_32ohm, 32},
{PHY_DDR3_RON_30ohm, 30},
{PHY_DDR3_RON_28ohm, 28},
@ -575,140 +573,142 @@ static const u16 d3_phy_drv_2_ohm[][2] = {
{PHY_DDR3_RON_25ohm, 25},
{PHY_DDR3_RON_24ohm, 24},
{PHY_DDR3_RON_23ohm, 23},
{PHY_DDR3_RON_22ohm, 22}
{PHY_DDR3_RON_22ohm, 22},
{PHY_DDR3_RON_21ohm, 21},
{PHY_DDR3_RON_20ohm, 20}
};
static u16 d3_phy_odt_2_ohm[][2] = {
{PHY_DDR3_RTT_DISABLE, 0},
{PHY_DDR3_RTT_953ohm, 953},
{PHY_DDR3_RTT_483ohm, 483},
{PHY_DDR3_RTT_320ohm, 320},
{PHY_DDR3_RTT_241ohm, 241},
{PHY_DDR3_RTT_193ohm, 193},
{PHY_DDR3_RTT_161ohm, 161},
{PHY_DDR3_RTT_138ohm, 138},
{PHY_DDR3_RTT_121ohm, 121},
{PHY_DDR3_RTT_107ohm, 107},
{PHY_DDR3_RTT_97ohm, 97},
{PHY_DDR3_RTT_88ohm, 88},
{PHY_DDR3_RTT_80ohm, 80},
{PHY_DDR3_RTT_74ohm, 74},
{PHY_DDR3_RTT_69ohm, 69},
{PHY_DDR3_RTT_561ohm, 561},
{PHY_DDR3_RTT_282ohm, 282},
{PHY_DDR3_RTT_188ohm, 188},
{PHY_DDR3_RTT_141ohm, 141},
{PHY_DDR3_RTT_113ohm, 113},
{PHY_DDR3_RTT_94ohm, 94},
{PHY_DDR3_RTT_81ohm, 81},
{PHY_DDR3_RTT_72ohm, 72},
{PHY_DDR3_RTT_64ohm, 64},
{PHY_DDR3_RTT_60ohm, 60},
{PHY_DDR3_RTT_57ohm, 57},
{PHY_DDR3_RTT_54ohm, 54},
{PHY_DDR3_RTT_51ohm, 51},
{PHY_DDR3_RTT_58ohm, 58},
{PHY_DDR3_RTT_52ohm, 52},
{PHY_DDR3_RTT_48ohm, 48},
{PHY_DDR3_RTT_46ohm, 46},
{PHY_DDR3_RTT_44ohm, 44},
{PHY_DDR3_RTT_42ohm, 42}
{PHY_DDR3_RTT_41ohm, 41},
{PHY_DDR3_RTT_38ohm, 38},
{PHY_DDR3_RTT_37ohm, 37},
{PHY_DDR3_RTT_34ohm, 34},
{PHY_DDR3_RTT_32ohm, 32},
{PHY_DDR3_RTT_31ohm, 31},
{PHY_DDR3_RTT_29ohm, 29},
{PHY_DDR3_RTT_28ohm, 28},
{PHY_DDR3_RTT_27ohm, 27},
{PHY_DDR3_RTT_25ohm, 25}
};
static u16 d4lp3_phy_drv_2_ohm[][2] = {
{PHY_DDR4_LPDDR3_RON_570ohm, 570},
{PHY_DDR4_LPDDR3_RON_285ohm, 285},
{PHY_DDR4_LPDDR3_RON_190ohm, 190},
{PHY_DDR4_LPDDR3_RON_142ohm, 142},
{PHY_DDR4_LPDDR3_RON_114ohm, 114},
{PHY_DDR4_LPDDR3_RON_95ohm, 95},
{PHY_DDR4_LPDDR3_RON_482ohm, 482},
{PHY_DDR4_LPDDR3_RON_244ohm, 244},
{PHY_DDR4_LPDDR3_RON_162ohm, 162},
{PHY_DDR4_LPDDR3_RON_122ohm, 122},
{PHY_DDR4_LPDDR3_RON_97ohm, 97},
{PHY_DDR4_LPDDR3_RON_81ohm, 81},
{PHY_DDR4_LPDDR3_RON_71ohm, 71},
{PHY_DDR4_LPDDR3_RON_63ohm, 63},
{PHY_DDR4_LPDDR3_RON_57ohm, 57},
{PHY_DDR4_LPDDR3_RON_52ohm, 52},
{PHY_DDR4_LPDDR3_RON_47ohm, 47},
{PHY_DDR4_LPDDR3_RON_69ohm, 69},
{PHY_DDR4_LPDDR3_RON_61ohm, 61},
{PHY_DDR4_LPDDR3_RON_54ohm, 54},
{PHY_DDR4_LPDDR3_RON_48ohm, 48},
{PHY_DDR4_LPDDR3_RON_44ohm, 44},
{PHY_DDR4_LPDDR3_RON_41ohm, 41},
{PHY_DDR4_LPDDR3_RON_38ohm, 38},
{PHY_DDR4_LPDDR3_RON_36ohm, 36},
{PHY_DDR4_LPDDR3_RON_40ohm, 40},
{PHY_DDR4_LPDDR3_RON_37ohm, 37},
{PHY_DDR4_LPDDR3_RON_34ohm, 34},
{PHY_DDR4_LPDDR3_RON_32ohm, 32},
{PHY_DDR4_LPDDR3_RON_30ohm, 30},
{PHY_DDR4_LPDDR3_RON_28ohm, 28},
{PHY_DDR4_LPDDR3_RON_27ohm, 27},
{PHY_DDR4_LPDDR3_RON_26ohm, 26},
{PHY_DDR4_LPDDR3_RON_25ohm, 25}
{PHY_DDR4_LPDDR3_RON_25ohm, 25},
{PHY_DDR4_LPDDR3_RON_24ohm, 24},
{PHY_DDR4_LPDDR3_RON_23ohm, 23},
{PHY_DDR4_LPDDR3_RON_22ohm, 22},
{PHY_DDR4_LPDDR3_RON_21ohm, 21}
};
static u16 d4lp3_phy_odt_2_ohm[][2] = {
{PHY_DDR4_LPDDR3_RTT_DISABLE, 0},
{PHY_DDR4_LPDDR3_RTT_973ohm, 973},
{PHY_DDR4_LPDDR3_RTT_493ohm, 493},
{PHY_DDR4_LPDDR3_RTT_327ohm, 327},
{PHY_DDR4_LPDDR3_RTT_247ohm, 247},
{PHY_DDR4_LPDDR3_RTT_197ohm, 197},
{PHY_DDR4_LPDDR3_RTT_164ohm, 164},
{PHY_DDR4_LPDDR3_RTT_141ohm, 141},
{PHY_DDR4_LPDDR3_RTT_123ohm, 123},
{PHY_DDR4_LPDDR3_RTT_109ohm, 109},
{PHY_DDR4_LPDDR3_RTT_586ohm, 586},
{PHY_DDR4_LPDDR3_RTT_294ohm, 294},
{PHY_DDR4_LPDDR3_RTT_196ohm, 196},
{PHY_DDR4_LPDDR3_RTT_148ohm, 148},
{PHY_DDR4_LPDDR3_RTT_118ohm, 118},
{PHY_DDR4_LPDDR3_RTT_99ohm, 99},
{PHY_DDR4_LPDDR3_RTT_90ohm, 90},
{PHY_DDR4_LPDDR3_RTT_82ohm, 82},
{PHY_DDR4_LPDDR3_RTT_85ohm, 58},
{PHY_DDR4_LPDDR3_RTT_76ohm, 76},
{PHY_DDR4_LPDDR3_RTT_70ohm, 70},
{PHY_DDR4_LPDDR3_RTT_66ohm, 66},
{PHY_DDR4_LPDDR3_RTT_62ohm, 62},
{PHY_DDR4_LPDDR3_RTT_58ohm, 58},
{PHY_DDR4_LPDDR3_RTT_67ohm, 67},
{PHY_DDR4_LPDDR3_RTT_60ohm, 60},
{PHY_DDR4_LPDDR3_RTT_55ohm, 55},
{PHY_DDR4_LPDDR3_RTT_52ohm, 52},
{PHY_DDR4_LPDDR3_RTT_49ohm, 49},
{PHY_DDR4_LPDDR3_RTT_47ohm, 47},
{PHY_DDR4_LPDDR3_RTT_45ohm, 45},
{PHY_DDR4_LPDDR3_RTT_43ohm, 43}
{PHY_DDR4_LPDDR3_RTT_50ohm, 50},
{PHY_DDR4_LPDDR3_RTT_46ohm, 46},
{PHY_DDR4_LPDDR3_RTT_43ohm, 43},
{PHY_DDR4_LPDDR3_RTT_40ohm, 40},
{PHY_DDR4_LPDDR3_RTT_38ohm, 38},
{PHY_DDR4_LPDDR3_RTT_36ohm, 36},
{PHY_DDR4_LPDDR3_RTT_34ohm, 34},
{PHY_DDR4_LPDDR3_RTT_32ohm, 32},
{PHY_DDR4_LPDDR3_RTT_31ohm, 31},
{PHY_DDR4_LPDDR3_RTT_29ohm, 29},
{PHY_DDR4_LPDDR3_RTT_28ohm, 28},
{PHY_DDR4_LPDDR3_RTT_27ohm, 27}
};
static u16 lp4_phy_drv_2_ohm[][2] = {
{PHY_LPDDR4_RON_606ohm, 606},
{PHY_LPDDR4_RON_303ohm, 303},
{PHY_LPDDR4_RON_202ohm, 202},
{PHY_LPDDR4_RON_152ohm, 153},
{PHY_LPDDR4_RON_121ohm, 121},
{PHY_LPDDR4_RON_501ohm, 501},
{PHY_LPDDR4_RON_253ohm, 253},
{PHY_LPDDR4_RON_168ohm, 168},
{PHY_LPDDR4_RON_126ohm, 126},
{PHY_LPDDR4_RON_101ohm, 101},
{PHY_LPDDR4_RON_87ohm, 87},
{PHY_LPDDR4_RON_76ohm, 76},
{PHY_LPDDR4_RON_67ohm, 67},
{PHY_LPDDR4_RON_61ohm, 61},
{PHY_LPDDR4_RON_55ohm, 55},
{PHY_LPDDR4_RON_51ohm, 51},
{PHY_LPDDR4_RON_47ohm, 47},
{PHY_LPDDR4_RON_43ohm, 43},
{PHY_LPDDR4_RON_40ohm, 40},
{PHY_LPDDR4_RON_84ohm, 84},
{PHY_LPDDR4_RON_72ohm, 72},
{PHY_LPDDR4_RON_63ohm, 63},
{PHY_LPDDR4_RON_56ohm, 56},
{PHY_LPDDR4_RON_50ohm, 50},
{PHY_LPDDR4_RON_46ohm, 46},
{PHY_LPDDR4_RON_42ohm, 42},
{PHY_LPDDR4_RON_38ohm, 38},
{PHY_LPDDR4_RON_36ohm, 36},
{PHY_LPDDR4_RON_34ohm, 34},
{PHY_LPDDR4_RON_32ohm, 32},
{PHY_LPDDR4_RON_30ohm, 30},
{PHY_LPDDR4_RON_33ohm, 33},
{PHY_LPDDR4_RON_31ohm, 31},
{PHY_LPDDR4_RON_29ohm, 29},
{PHY_LPDDR4_RON_28ohm, 28},
{PHY_LPDDR4_RON_26ohm, 26}
{PHY_LPDDR4_RON_26ohm, 26},
{PHY_LPDDR4_RON_25ohm, 25},
{PHY_LPDDR4_RON_24ohm, 24},
{PHY_LPDDR4_RON_23ohm, 23},
{PHY_LPDDR4_RON_22ohm, 22}
};
static u16 lp4_phy_odt_2_ohm[][2] = {
{PHY_LPDDR4_RTT_DISABLE, 0},
{PHY_LPDDR4_RTT_998ohm, 998},
{PHY_LPDDR4_RTT_506ohm, 506},
{PHY_LPDDR4_RTT_336ohm, 336},
{PHY_LPDDR4_RTT_253ohm, 253},
{PHY_LPDDR4_RTT_604ohm, 604},
{PHY_LPDDR4_RTT_303ohm, 303},
{PHY_LPDDR4_RTT_202ohm, 202},
{PHY_LPDDR4_RTT_169ohm, 169},
{PHY_LPDDR4_RTT_144ohm, 144},
{PHY_LPDDR4_RTT_127ohm, 127},
{PHY_LPDDR4_RTT_112ohm, 112},
{PHY_LPDDR4_RTT_152ohm, 152},
{PHY_LPDDR4_RTT_122ohm, 122},
{PHY_LPDDR4_RTT_101ohm, 101},
{PHY_LPDDR4_RTT_92ohm, 92},
{PHY_LPDDR4_RTT_84ohm, 84},
{PHY_LPDDR4_RTT_87ohm, 87},
{PHY_LPDDR4_RTT_78ohm, 78},
{PHY_LPDDR4_RTT_72ohm, 72},
{PHY_LPDDR4_RTT_67ohm, 67},
{PHY_LPDDR4_RTT_63ohm, 63},
{PHY_LPDDR4_RTT_60ohm, 60},
{PHY_LPDDR4_RTT_69ohm, 69},
{PHY_LPDDR4_RTT_62ohm, 62},
{PHY_LPDDR4_RTT_56ohm, 56},
{PHY_LPDDR4_RTT_53ohm, 53},
{PHY_LPDDR4_RTT_51ohm, 51},
{PHY_LPDDR4_RTT_52ohm, 52},
{PHY_LPDDR4_RTT_48ohm, 48},
{PHY_LPDDR4_RTT_46ohm, 46},
{PHY_LPDDR4_RTT_44ohm, 44}
{PHY_LPDDR4_RTT_44ohm, 44},
{PHY_LPDDR4_RTT_41ohm, 41},
{PHY_LPDDR4_RTT_39ohm, 39},
{PHY_LPDDR4_RTT_37ohm, 37},
{PHY_LPDDR4_RTT_35ohm, 35},
{PHY_LPDDR4_RTT_33ohm, 33},
{PHY_LPDDR4_RTT_32ohm, 32},
{PHY_LPDDR4_RTT_30ohm, 30},
{PHY_LPDDR4_RTT_29ohm, 29},
{PHY_LPDDR4_RTT_27ohm, 27}
};
static u32 lp4_odt_calc(u32 odt_ohm)
@ -1464,7 +1464,7 @@ static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype)
if (dramtype != LPDDR4) {
for (i = 0; i < 4; i++) {
j = 0x110 + i * 0x10;
writel(PHY_DDR4_LPDDR3_RTT_247ohm,
writel(PHY_DDR4_LPDDR3_RTT_294ohm,
PHY_REG(phy_base, j));
writel(PHY_DDR4_LPDDR3_RTT_DISABLE,
PHY_REG(phy_base, j + 0x1));