From 6b7c0aa59e7763ce34b2f17d13496a0a4327e956 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 12 Oct 2020 14:50:28 +0800 Subject: [PATCH] rockchip: dts: rk3568: sync from kernel sync from: ac723c clk: rockchip: rk3568: Replace RKNN with NPU Change-Id: I24084626ef787f6fb7cbb8875365eb31fbea3541 Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3568-cru.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h index 176e124512..7f9290809c 100644 --- a/include/dt-bindings/clock/rk3568-cru.h +++ b/include/dt-bindings/clock/rk3568-cru.h @@ -97,8 +97,8 @@ #define HCLK_NPU_PRE 37 #define PCLK_NPU_PRE 38 #define ACLK_NPU_PRE 39 -#define ACLK_RKNN 40 -#define HCLK_RKNN 41 +#define ACLK_NPU 40 +#define HCLK_NPU 41 #define PCLK_NPU_PVTM 42 #define CLK_NPU_PVTM 43 #define CLK_NPU_PVTM_CORE 44 @@ -460,8 +460,10 @@ #define SCLK_SDMMC2_SAMPLE 399 #define SCLK_EMMC_DRV 400 #define SCLK_EMMC_SAMPLE 401 +#define PCLK_EDPPHY_GRF 402 +#define PCLK_CORE_PVTM 403 -#define CLK_NR_CLKS (SCLK_EMMC_SAMPLE + 1) +#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) /* pmu soft-reset indices */ /* pmucru_softrst_con0 */ @@ -521,8 +523,8 @@ #define SRST_A_NPU_NIU 40 #define SRST_H_NPU_NIU 41 #define SRST_P_NPU_NIU 42 -#define SRST_A_RKNN 43 -#define SRST_H_RKNN 44 +#define SRST_A_NPU 43 +#define SRST_H_NPU 44 #define SRST_P_NPU_PVTM 45 #define SRST_NPU_PVTM 46 #define SRST_NPU_PVTPLL 47