sound: rockchip: add support for i2s
This patch add driver support for rockchip i2s bus. Change-Id: I2c7f2b46d628706fa000055f7962ba6b4ff6d0b6 Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
Jianhong Chen
parent
95f2641240
commit
69ab2873d7
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@ -31,6 +31,16 @@ config I2S_SAMSUNG
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option provides an implementation for sound_init() and
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sound_play().
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config I2S_ROCKCHIP
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bool "Enable I2S support for rockchip SoCs"
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depends on SOUND
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help
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Rockchip SoCs support an I2S interface for sending audio
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data to an audio codec. This option enables support for this,
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using one of the available audio codec drivers. Enabling this
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option provides an implementation for sound_init() and
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sound_play().
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config SOUND_MAX98095
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bool "Support Maxim max98095 audio codec"
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depends on I2S_SAMSUNG
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@ -7,6 +7,7 @@
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obj-$(CONFIG_SOUND) += sound.o
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obj-$(CONFIG_I2S) += sound-i2s.o
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obj-$(CONFIG_I2S_ROCKCHIP) += rockchip-i2s.o
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obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o
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obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o
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obj-$(CONFIG_SOUND_WM8994) += wm8994.o
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@ -0,0 +1,189 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <sound.h>
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#include "rockchip-i2s.h"
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#define I2S_FIFO_LENGTH (31)
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struct rk_i2s_dev {
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void *regbase;
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struct clk mclk;
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};
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static inline u32 i2s_reg_readl(struct rk_i2s_dev *dev, u32 offset)
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{
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return readl(dev->regbase + offset);
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}
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static inline void i2s_reg_writel(struct rk_i2s_dev *dev, u32 offset, u32 val)
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{
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writel(val, dev->regbase + offset);
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}
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static inline void i2s_reg_update_bits(struct rk_i2s_dev *dev, u32 offset,
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u32 mask, u32 val)
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{
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u32 tmp, orig;
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orig = readl(dev->regbase + offset);
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tmp = orig & ~mask;
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tmp |= val & mask;
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if (tmp != orig)
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writel(tmp, dev->regbase + offset);
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}
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static void dump_regs(struct rk_i2s_dev *dev)
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{
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int i = 0;
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for (i = 0; i <= I2S_RXDR; i += 4)
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debug("0x%02x: 0x%08x\n", i, readl(dev->regbase + i));
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}
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static int rk_i2s_hw_params(struct udevice *udev, unsigned int samplerate,
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unsigned int fmt, unsigned int channels)
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{
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struct rk_i2s_dev *dev = dev_get_priv(udev);
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/* set fmt */
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i2s_reg_update_bits(dev, I2S_CKR,
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I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
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i2s_reg_update_bits(dev, I2S_TXCR,
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I2S_TXCR_IBM_MASK, I2S_TXCR_IBM_NORMAL);
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i2s_reg_update_bits(dev, I2S_RXCR,
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I2S_RXCR_IBM_MASK, I2S_RXCR_IBM_NORMAL);
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/* set div */
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i2s_reg_update_bits(dev, I2S_CKR,
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I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
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I2S_CKR_TSD(64) | I2S_CKR_RSD(64));
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i2s_reg_update_bits(dev, I2S_CKR,
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I2S_CKR_MDIV_MASK, I2S_CKR_MDIV(4));
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/* set hwparams */
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i2s_reg_update_bits(dev, I2S_TXCR,
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I2S_TXCR_VDW_MASK |
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I2S_TXCR_CSR_MASK,
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I2S_TXCR_VDW(16) |
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I2S_TXCR_CHN_2);
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i2s_reg_update_bits(dev, I2S_RXCR,
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I2S_RXCR_CSR_MASK |
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I2S_RXCR_VDW_MASK,
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I2S_TXCR_VDW(16) |
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I2S_TXCR_CHN_2);
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i2s_reg_update_bits(dev, I2S_DMACR,
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I2S_DMACR_TDL_MASK | I2S_DMACR_RDL_MASK,
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I2S_DMACR_TDL(16) | I2S_DMACR_RDL(16));
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return 0;
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}
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static void rk_i2s_txctrl(struct rk_i2s_dev *dev, int on)
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{
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if (on) {
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i2s_reg_update_bits(dev, I2S_XFER,
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I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START);
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} else {
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i2s_reg_update_bits(dev, I2S_XFER,
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I2S_XFER_TXS_MASK |
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I2S_XFER_RXS_MASK,
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I2S_XFER_TXS_STOP |
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I2S_XFER_RXS_STOP);
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i2s_reg_update_bits(dev, I2S_CLR,
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I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
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I2S_CLR_TXC | I2S_CLR_RXC);
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}
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}
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static int rk_i2s_transfer_tx_data(struct udevice *udev, unsigned int *data,
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unsigned long data_size)
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{
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struct rk_i2s_dev *dev = dev_get_priv(udev);
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u32 val;
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if (data_size < I2S_FIFO_LENGTH) {
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debug("%s : invalid data size\n", __func__);
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return -EINVAL;
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}
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rk_i2s_txctrl(dev, 1);
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while (data_size > 0) {
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val = i2s_reg_readl(dev, I2S_FIFOLR);
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if (val < I2S_FIFO_LENGTH) {
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i2s_reg_writel(dev, I2S_TXDR, *data++);
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data_size--;
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}
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}
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return 0;
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}
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static int rk_i2s_set_sysclk(struct udevice *dev, unsigned int freq)
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{
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struct rk_i2s_dev *i2s = dev_get_priv(dev);
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clk_set_rate(&i2s->mclk, freq);
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return 0;
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}
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static const struct snd_soc_dai_ops rockchip_i2s_ops = {
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.hw_params = rk_i2s_hw_params,
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.set_sysclk = rk_i2s_set_sysclk,
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.transfer = rk_i2s_transfer_tx_data,
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};
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static int rockchip_i2s_probe(struct udevice *dev)
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{
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struct rk_i2s_dev *i2s = dev_get_priv(dev);
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int ret;
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i2s->regbase = dev_read_addr_ptr(dev);
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ret = clk_get_by_name(dev, "i2s_clk", &i2s->mclk);
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if (ret) {
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printf("%s get i2s mclk fail!\n", __func__);
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return -EINVAL;
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}
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dump_regs(i2s);
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return 0;
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}
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static const struct udevice_id rockchip_i2s_ids[] = {
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{ .compatible = "rockchip,px30-i2s", },
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{ .compatible = "rockchip,rk3036-i2s", },
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{ .compatible = "rockchip,rk3066-i2s", },
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{ .compatible = "rockchip,rk3128-i2s", },
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{ .compatible = "rockchip,rk3188-i2s", },
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{ .compatible = "rockchip,rk3288-i2s", },
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{ .compatible = "rockchip,rk3328-i2s", },
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{ .compatible = "rockchip,rk3368-i2s", },
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{ .compatible = "rockchip,rk3399-i2s", },
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{ }
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};
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U_BOOT_DRIVER(rockchip_i2s) = {
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.name = "rockchip_i2s",
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.id = UCLASS_I2S,
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.of_match = rockchip_i2s_ids,
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.probe = rockchip_i2s_probe,
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.priv_auto_alloc_size = sizeof(struct rk_i2s_dev),
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.ops = &rockchip_i2s_ops,
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};
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UCLASS_DRIVER(i2s) = {
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.id = UCLASS_I2S,
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.name = "i2s_bus",
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};
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@ -0,0 +1,209 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd
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*/
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#ifndef __ROCKCHIP_I2S_H__
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#define __ROCKCHIP_I2S_H__
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/* I2S REGS */
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#define I2S_TXCR (0x0000)
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#define I2S_RXCR (0x0004)
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#define I2S_CKR (0x0008)
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#define I2S_FIFOLR (0x000c)
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#define I2S_DMACR (0x0010)
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#define I2S_INTCR (0x0014)
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#define I2S_INTSR (0x0018)
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#define I2S_XFER (0x001c)
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#define I2S_CLR (0x0020)
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#define I2S_TXDR (0x0024)
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#define I2S_RXDR (0x0028)
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/*
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* TXCR
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* transmit operation control register
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*/
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#define I2S_TXCR_RCNT_SHIFT 17
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#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
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#define I2S_TXCR_CSR_SHIFT 15
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#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_2 (0 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_4 (1 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_6 (2 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CHN_8 (3 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_HWT BIT(14)
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#define I2S_TXCR_SJM_SHIFT 12
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#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
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#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
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#define I2S_TXCR_FBM_SHIFT 11
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#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
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#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
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#define I2S_TXCR_IBM_SHIFT 9
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#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_PBM_SHIFT 7
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#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
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#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
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#define I2S_TXCR_TFS_SHIFT 5
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#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_VDW_SHIFT 0
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#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
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#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
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/*
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* RXCR
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* receive operation control register
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*/
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#define I2S_RXCR_CSR_SHIFT 15
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#define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT)
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#define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
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#define I2S_RXCR_HWT BIT(14)
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#define I2S_RXCR_SJM_SHIFT 12
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#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
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#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
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#define I2S_RXCR_FBM_SHIFT 11
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#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
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#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
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#define I2S_RXCR_IBM_SHIFT 9
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#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_PBM_SHIFT 7
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#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
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#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
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#define I2S_RXCR_TFS_SHIFT 5
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#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_VDW_SHIFT 0
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#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
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#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
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/*
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* CKR
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* clock generation register
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*/
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#define I2S_CKR_MSS_SHIFT 27
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#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_CKP_SHIFT 26
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#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_RLP_SHIFT 25
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#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_TLP_SHIFT 24
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#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
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#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
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#define I2S_CKR_MDIV_SHIFT 16
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#define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT)
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#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
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#define I2S_CKR_RSD_SHIFT 8
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#define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT)
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#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
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#define I2S_CKR_TSD_SHIFT 0
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#define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT)
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#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
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/*
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* FIFOLR
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* FIFO level register
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*/
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#define I2S_FIFOLR_RFL_SHIFT 24
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#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
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#define I2S_FIFOLR_TFL3_SHIFT 18
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#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
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#define I2S_FIFOLR_TFL2_SHIFT 12
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#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
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#define I2S_FIFOLR_TFL1_SHIFT 6
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#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
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#define I2S_FIFOLR_TFL0_SHIFT 0
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#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
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/*
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* DMACR
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* DMA control register
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*/
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#define I2S_DMACR_RDE_SHIFT 24
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#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDE_MASK (1 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDL_SHIFT 16
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#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
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#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
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#define I2S_DMACR_TDE_SHIFT 8
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#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDE_MASK (1 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDL_SHIFT 0
|
||||
#define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
|
||||
#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
|
||||
|
||||
/*
|
||||
* INTCR
|
||||
* interrupt control register
|
||||
*/
|
||||
#define I2S_INTCR_RFT_SHIFT 20
|
||||
#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
|
||||
#define I2S_INTCR_RXOIC BIT(18)
|
||||
#define I2S_INTCR_RXOIE_SHIFT 17
|
||||
#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
|
||||
#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
|
||||
#define I2S_INTCR_RXFIE_SHIFT 16
|
||||
#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
|
||||
#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
|
||||
#define I2S_INTCR_TFT_SHIFT 4
|
||||
#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
|
||||
#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
|
||||
#define I2S_INTCR_TXUIC BIT(2)
|
||||
#define I2S_INTCR_TXUIE_SHIFT 1
|
||||
#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
|
||||
#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
|
||||
|
||||
/*
|
||||
* INTSR
|
||||
* interrupt status register
|
||||
*/
|
||||
#define I2S_INTSR_RXOI_SHIFT 17
|
||||
#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
|
||||
#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
|
||||
#define I2S_INTSR_RXFI_SHIFT 16
|
||||
#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
|
||||
#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
|
||||
#define I2S_INTSR_TXUI_SHIFT 1
|
||||
#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
|
||||
#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
|
||||
#define I2S_INTSR_TXEI_SHIFT 0
|
||||
#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
|
||||
#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
|
||||
|
||||
/*
|
||||
* XFER
|
||||
* Transfer start register
|
||||
*/
|
||||
#define I2S_XFER_RXS_SHIFT 1
|
||||
#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_RXS_MASK (1 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_TXS_SHIFT 0
|
||||
#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
|
||||
#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
|
||||
#define I2S_XFER_TXS_MASK (1 << I2S_XFER_TXS_SHIFT)
|
||||
|
||||
/*
|
||||
* CLR
|
||||
* clear SCLK domain logic register
|
||||
*/
|
||||
#define I2S_CLR_RXC BIT(1)
|
||||
#define I2S_CLR_RXC_MASK BIT(1)
|
||||
#define I2S_CLR_TXC BIT(0)
|
||||
#define I2S_CLR_TXC_MASK BIT(0)
|
||||
|
||||
#endif
|
||||
|
|
@ -41,6 +41,7 @@ enum uclass_id {
|
|||
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
|
||||
UCLASS_I2C_GENERIC, /* Generic I2C device */
|
||||
UCLASS_I2C_MUX, /* I2C multiplexer */
|
||||
UCLASS_I2S, /* I2S bus */
|
||||
UCLASS_IDE, /* IDE device */
|
||||
UCLASS_IRQ, /* Interrupt controller */
|
||||
UCLASS_KEYBOARD, /* Keyboard input device */
|
||||
|
|
|
|||
|
|
@ -53,4 +53,14 @@ int sound_init(const void *blob);
|
|||
*/
|
||||
int sound_play(uint32_t msec, uint32_t frequency);
|
||||
|
||||
struct snd_soc_dai_ops {
|
||||
int (*hw_params)(struct udevice *dev, unsigned int samplerate,
|
||||
unsigned int fmt, unsigned int channels);
|
||||
int (*startup)(struct udevice *dev);
|
||||
int (*shutdown)(struct udevice *dev);
|
||||
int (*transfer)(struct udevice *dev, unsigned int *data,
|
||||
unsigned long data_size);
|
||||
int (*set_sysclk)(struct udevice *dev, unsigned int freq);
|
||||
};
|
||||
|
||||
#endif /* __SOUND__H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue