video/drm: analogix_dp: Add support for rk3568
This patch adds support for Analogix eDP TX IP used on RK3568 SoC. Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: Ia48f1f99f336d4d98d5fba4e5fd15a35bdbaf373
This commit is contained in:
Wyon Bi
parent
c5b1fb658e
commit
699c29a5d8
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@ -27,13 +27,15 @@
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* @lcdsel_grf_reg: grf register offset of lcdc select
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* @lcdsel_big: reg value of selecting vop big for eDP
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* @lcdsel_lit: reg value of selecting vop little for eDP
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* @chip_type: specific chip type
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* @ssc: check if SSC is supported by source
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*/
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struct rockchip_dp_chip_data {
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u32 lcdsel_grf_reg;
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u32 lcdsel_big;
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u32 lcdsel_lit;
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u32 chip_type;
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bool has_vop_sel;
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bool ssc;
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};
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static void
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@ -105,6 +107,14 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
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if (retval)
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return retval;
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/* Spread AMP if required, enable 8b/10b coding */
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buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0;
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buf[1] = DP_SET_ANSI_8B10B;
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retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL,
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2, buf);
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if (retval < 0)
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return retval;
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/* Set TX voltage-swing and pre-emphasis to minimum */
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for (lane = 0; lane < lane_count; lane++)
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dp->link_train.training_lane[lane] =
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@ -397,6 +407,8 @@ static int analogix_dp_init_training(struct analogix_dp_device *dp,
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enum link_lane_count_type max_lane,
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int max_rate)
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{
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u8 dpcd;
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/*
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* MACRO_RST must be applied after the PLL_LOCK to avoid
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* the DP inter pair skew issue for at least 10 us
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@ -425,6 +437,9 @@ static int analogix_dp_init_training(struct analogix_dp_device *dp,
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if (dp->link_train.link_rate > max_rate)
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dp->link_train.link_rate = max_rate;
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analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd);
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dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);
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/* All DP analog module power up */
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analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
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@ -721,14 +736,15 @@ static int analogix_dp_connector_init(struct display_state *state)
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struct analogix_dp_device *dp = dev_get_priv(conn_state->dev);
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conn_state->type = DRM_MODE_CONNECTOR_eDP;
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conn_state->output_if |= VOP_OUTPUT_IF_eDP0;
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conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
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conn_state->color_space = V4L2_COLORSPACE_DEFAULT;
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/* eDP software reset request */
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reset_assert(&dp->reset);
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reset_assert_bulk(&dp->resets);
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udelay(1);
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reset_deassert(&dp->reset);
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reset_deassert_bulk(&dp->resets);
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generic_phy_power_on(&dp->phy);
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analogix_dp_init_dp(dp);
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return 0;
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@ -762,13 +778,13 @@ static int analogix_dp_connector_enable(struct display_state *state)
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u32 val;
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int ret;
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if (pdata->has_vop_sel) {
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if (pdata->lcdsel_grf_reg) {
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if (crtc_state->crtc_id)
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val = pdata->lcdsel_lit;
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else
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val = pdata->lcdsel_big;
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writel(val, dp->grf + pdata->lcdsel_grf_reg);
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writel(val, syscon_get_first_range(ROCKCHIP_SYSCON_GRF) + pdata->lcdsel_grf_reg);
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}
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switch (conn_state->bpc) {
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@ -840,11 +856,8 @@ static int analogix_dp_probe(struct udevice *dev)
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int ret;
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dp->reg_base = dev_read_addr_ptr(dev);
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dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(dp->grf))
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return PTR_ERR(dp->grf);
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ret = reset_get_by_name(dev, "dp", &dp->reset);
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ret = reset_get_bulk(dev, &dp->resets);
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if (ret) {
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dev_err(dev, "failed to get reset control: %d\n", ret);
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return ret;
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@ -857,10 +870,13 @@ static int analogix_dp_probe(struct udevice *dev)
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return ret;
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}
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generic_phy_get_by_name(dev, "dp", &dp->phy);
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dp->force_hpd = dev_read_bool(dev, "force-hpd");
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dp->plat_data.dev_type = ROCKCHIP_DP;
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dp->plat_data.subdev_type = pdata->chip_type;
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dp->plat_data.ssc = pdata->ssc;
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/*
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* Like Rockchip DisplayPort TRM indicate that "Main link
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* containing 4 physical lanes of 2.7/1.62 Gbps/lane".
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@ -878,7 +894,6 @@ static const struct rockchip_dp_chip_data rk3288_edp_platform_data = {
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.lcdsel_big = 0 | BIT(21),
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.lcdsel_lit = BIT(5) | BIT(21),
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.chip_type = RK3288_DP,
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.has_vop_sel = true,
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};
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static const struct rockchip_connector rk3288_edp_driver_data = {
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@ -888,7 +903,6 @@ static const struct rockchip_connector rk3288_edp_driver_data = {
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static const struct rockchip_dp_chip_data rk3368_edp_platform_data = {
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.chip_type = RK3368_EDP,
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.has_vop_sel = false,
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};
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static const struct rockchip_connector rk3368_edp_driver_data = {
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@ -901,7 +915,6 @@ static const struct rockchip_dp_chip_data rk3399_edp_platform_data = {
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.lcdsel_big = 0 | BIT(21),
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.lcdsel_lit = BIT(5) | BIT(21),
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.chip_type = RK3399_EDP,
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.has_vop_sel = true,
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};
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static const struct rockchip_connector rk3399_edp_driver_data = {
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@ -909,6 +922,16 @@ static const struct rockchip_connector rk3399_edp_driver_data = {
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.data = &rk3399_edp_platform_data,
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};
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static const struct rockchip_dp_chip_data rk3568_edp_platform_data = {
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.chip_type = RK3568_EDP,
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.ssc = true,
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};
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static const struct rockchip_connector rk3568_edp_driver_data = {
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.funcs = &analogix_dp_connector_funcs,
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.data = &rk3568_edp_platform_data,
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};
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static const struct udevice_id analogix_dp_ids[] = {
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{
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.compatible = "rockchip,rk3288-dp",
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@ -919,6 +942,9 @@ static const struct udevice_id analogix_dp_ids[] = {
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}, {
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.compatible = "rockchip,rk3399-edp",
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.data = (ulong)&rk3399_edp_driver_data,
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}, {
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.compatible = "rockchip,rk3568-edp",
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.data = (ulong)&rk3568_edp_driver_data,
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},
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{}
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};
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@ -7,6 +7,7 @@
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#ifndef __DRM_ANALOGIX_DP_H__
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#define __DRM_ANALOGIX_DP_H__
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#include <generic-phy.h>
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#include <reset.h>
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#include <drm/drm_dp_helper.h>
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@ -515,6 +516,7 @@ struct link_train {
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u8 link_rate;
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u8 lane_count;
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u8 training_lane[4];
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bool ssc;
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enum link_training_state lt_state;
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};
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@ -528,18 +530,20 @@ enum analogix_dp_sub_devtype {
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RK3288_DP,
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RK3368_EDP,
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RK3399_EDP,
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RK3568_EDP,
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};
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struct analogix_dp_plat_data {
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enum analogix_dp_devtype dev_type;
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enum analogix_dp_sub_devtype subdev_type;
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bool ssc;
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};
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struct analogix_dp_device {
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struct udevice *dev;
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void *reg_base;
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void *grf;
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struct reset_ctl reset;
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struct phy phy;
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struct reset_ctl_bulk resets;
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struct gpio_desc hpd_gpio;
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bool force_hpd;
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struct video_info video_info;
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@ -628,5 +632,6 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
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void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
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void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
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void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
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bool analogix_dp_ssc_supported(struct analogix_dp_device *dp);
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#endif /* __DRM_ANALOGIX_DP__ */
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@ -906,8 +906,15 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
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return retval;
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}
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bool analogix_dp_ssc_supported(struct analogix_dp_device *dp)
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{
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/* Check if SSC is supported by both sides */
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return dp->plat_data.ssc && dp->link_train.ssc;
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}
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void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
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{
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union phy_configure_opts phy_cfg;
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u32 reg, status;
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int ret;
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@ -915,6 +922,20 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
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if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
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analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg);
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phy_cfg.dp.lanes = dp->link_train.lane_count;
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phy_cfg.dp.link_rate =
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drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
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phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
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phy_cfg.dp.set_lanes = false;
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phy_cfg.dp.set_rate = true;
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phy_cfg.dp.set_voltages = false;
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ret = generic_phy_configure(&dp->phy, &phy_cfg);
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if (ret) {
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dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
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__func__, ret);
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return;
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}
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ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
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status != PLL_UNLOCKED,
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120 * DP_TIMEOUT_LOOP_COUNT);
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@ -934,10 +955,23 @@ void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
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void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
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{
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union phy_configure_opts phy_cfg;
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u32 reg;
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int ret;
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reg = count;
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analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg);
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phy_cfg.dp.lanes = dp->link_train.lane_count;
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phy_cfg.dp.set_lanes = true;
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phy_cfg.dp.set_rate = false;
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phy_cfg.dp.set_voltages = false;
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ret = generic_phy_configure(&dp->phy, &phy_cfg);
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if (ret) {
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dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
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__func__, ret);
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return;
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}
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}
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void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
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@ -950,12 +984,36 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
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void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
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{
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union phy_configure_opts phy_cfg;
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u8 lane;
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int ret;
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for (lane = 0; lane < dp->link_train.lane_count; lane++) {
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u8 training_lane = dp->link_train.training_lane[lane];
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u8 vs, pe;
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for (lane = 0; lane < dp->link_train.lane_count; lane++)
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analogix_dp_write(dp,
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ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane,
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dp->link_train.training_lane[lane]);
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vs = (training_lane >> DP_TRAIN_VOLTAGE_SWING_SHIFT) &
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DP_TRAIN_VOLTAGE_SWING_MASK;
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pe = (training_lane >> DP_TRAIN_PRE_EMPHASIS_SHIFT) &
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DP_TRAIN_PRE_EMPHASIS_MASK;
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phy_cfg.dp.voltage[lane] = vs;
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phy_cfg.dp.pre[lane] = pe;
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}
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phy_cfg.dp.lanes = dp->link_train.lane_count;
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phy_cfg.dp.set_lanes = false;
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phy_cfg.dp.set_rate = false;
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phy_cfg.dp.set_voltages = true;
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ret = generic_phy_configure(&dp->phy, &phy_cfg);
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if (ret) {
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dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
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__func__, ret);
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return;
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}
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}
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u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane)
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