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UPSTREAM: net: dwc_eth_qos: Flush the RX descriptors on init 

Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7a37f8a1fd51b2b7ca4fb557885d711ebd72c49c
This commit is contained in:
Marek Vasut 2020-03-23 02:09:01 +01:00 committed by Joseph Chen
parent 364f8fdc57
commit 6399c699b8
1 changed files with 1 additions and 1 deletions
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2
drivers/net/dwc_eth_qos.c
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@ -1288,8 +1288,8 @@ static int eqos_start(struct udevice *dev)
rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
(i * EQOS_MAX_PACKET_SIZE));
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
eqos->config->ops->eqos_flush_desc(rx_desc);
}
eqos->config->ops->eqos_flush_desc(eqos->descs);
writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);