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UPSTREAM: usb: dwc2_udc_otg: Add tx_fifo_sz array support 

All TX fifo size can be different, add tx_fifo_sz_array[]
into dwc2_plat_otg_data to be able to set them.

tx_fifo_sz_array[] is 17 Bytes long and can contains max 16
tx fifo size (synopsys IP supports max 16 IN endpoints).
First entry of tx_fifo_sz_array[] is the number of valid
fifo size the array contains.

In case of tx_fifo_sz_array[] doesn't contains the same
number of element than max hardware endpoint, display
a warning message.

Compatibility with board which doesn't use tx_fifo_sz_array[]
(Rockchip rk322x/rk3128/rv1108/rk3288/rk3036) is kept.

Change-Id: If32954770f9571a1bb18376239ef9cff9a721178
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 763bb106f66c147b7d0c3046dbba66a07d7a9dd2)
This commit is contained in:
Patrice Chotard 2019-03-29 15:42:20 +01:00 committed by Frank Wang
parent 38b0d5741a
commit 6187c34651
2 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/usb/gadget/dwc2_udc_otg.c
View File

@ -459,6 +459,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
uint32_t dflt_gusbcfg;
uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
u32 max_hw_ep;
int pdata_hw_ep;
debug("Reseting OTG controller\n");
@ -544,11 +545,20 @@ static void reconfig_usbd(struct dwc2_udc *dev)
/* retrieve the number of IN Endpoints (excluding ep0) */
max_hw_ep = (readl(&reg->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
GHWCFG4_NUM_IN_EPS_SHIFT;
pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
/* tx_fifo_sz_nb should equal to number of IN Endpoint */
if (pdata_hw_ep && max_hw_ep != pdata_hw_ep)
pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n",
max_hw_ep, pdata_hw_ep);
for (i = 0; i < max_hw_ep; i++) {
if (pdata_hw_ep)
tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
for (i = 0; i < max_hw_ep; i++)
writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
tx_fifo_sz << 16, &reg->dieptxf[i]);
}
/* Flush the RX FIFO */
writel(RX_FIFO_FLUSH, &reg->grstctl);
while (readl(&reg->grstctl) & RX_FIFO_FLUSH)

3
include/usb/dwc2_udc.h
View File

@ -10,6 +10,7 @@
#define __DWC2_USB_GADGET
#define PHY0_SLEEP (1 << 5)
#define DWC2_MAX_HW_ENDPOINTS 16
struct dwc2_plat_otg_data {
void *priv;
@ -23,6 +24,8 @@ struct dwc2_plat_otg_data {
unsigned int rx_fifo_sz;
unsigned int np_tx_fifo_sz;
unsigned int tx_fifo_sz;
unsigned int tx_fifo_sz_array[DWC2_MAX_HW_ENDPOINTS];
unsigned char tx_fifo_sz_nb;
bool force_b_session_valid;
};