rockchip: rk3568: support usbplug
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: If2c56d1db774f79689cfbe87bcae7cfcadacae82
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@ -385,7 +385,7 @@ config ROCKCHIP_RK3568
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bool "Support Rockchip RK3568"
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select ARM64 if !ARM64_BOOT_AARCH32
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select ARM_SMCCC
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select GICV3 if !ARM64_BOOT_AARCH32
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select GICV3 if !ARM64_BOOT_AARCH32 && !SUPPORT_USBPLUG
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select SUPPORT_TPL if !ARM64_BOOT_AARCH32
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select SUPPORT_SPL if !ARM64_BOOT_AARCH32
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select TPL_TINY_FRAMEWORK if TPL
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@ -16,6 +16,11 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PMUGRF_BASE 0xfdc20000
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#define GRF_BASE 0xfdc60000
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#define GRF_GPIO1B_IOMUX_H 0x0C
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#define GRF_GPIO1C_IOMUX_L 0x10
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#define GRF_GPIO1C_IOMUX_H 0x14
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#define GRF_GPIO1D_IOMUX_L 0x18
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#define GRF_GPIO1D_IOMUX_H 0x1C
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#define GRF_GPIO1B_DS_2 0x218
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#define GRF_GPIO1B_DS_3 0x21c
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#define GRF_GPIO1C_DS_0 0x220
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@ -863,6 +868,35 @@ int arch_cpu_init(void)
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#ifndef CONFIG_TPL_BUILD
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qos_priority_init();
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#endif
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#elif defined(CONFIG_SUPPORT_USBPLUG)
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/*
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* When perform idle operation, corresponding clock can
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* be opened or gated automatically.
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*/
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writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
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writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
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writel(0x00030000, SGRF_BASE + SGRF_SOC_CON4); /* usb3otg0 master secure setting */
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/* Set the emmc sdmmc0 to secure */
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writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
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/* set the emmc ds to level 2 */
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
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/* emmc and sfc iomux */
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writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
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writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
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writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
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writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
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writel(((7 << 0) << 16) | (1 << 0), GRF_BASE + GRF_GPIO1D_IOMUX_H);
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/* Set the fspi to secure */
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writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
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#endif
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return 0;
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@ -19,7 +19,13 @@
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#ifdef CONFIG_SUPPORT_USBPLUG
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x00a00000
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
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#define CONFIG_SYS_LOAD_ADDR 0x00c00800
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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