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rockchip: resource: add gpio-v2 support for hw-id dtb 

It's for rv1126/rk356x.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic5a58483e43154c8ba61be466214f87753e47dd3
This commit is contained in:
Joseph Chen 2021-01-11 02:40:39 +00:00
parent a39ea68564
commit 5e0c61290d
1 changed files with 52 additions and 27 deletions
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79
arch/arm/mach-rockchip/resource_img.c
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@ -586,11 +586,48 @@ int rockchip_read_resource_file(void *buf, const char *name,
#define KEY_WORDS_ADC_CTRL "#_" #define KEY_WORDS_ADC_CTRL "#_"
#define KEY_WORDS_ADC_CH "_ch" #define KEY_WORDS_ADC_CH "_ch"
#define KEY_WORDS_GPIO "#gpio" #define KEY_WORDS_GPIO "#gpio"
#define GPIO_SWPORT_DDR 0x04
#define GPIO_EXT_PORT 0x50
#define MAX_ADC_CH_NR 10 #define MAX_ADC_CH_NR 10
#define MAX_GPIO_NR 10 #define MAX_GPIO_NR 10
#ifdef CONFIG_ROCKCHIP_GPIO_V2
#define GPIO_SWPORT_DDR 0x08
#define GPIO_EXT_PORT 0x70
#define WMSK_SETBIT(n) (n << 16 | n)
#define WMSK_CLRBIT(n) (n << 16)
#define REG_PLUS4(off, n) (off + (n >= BIT(16) ? 4 : 0))
#define BIT_SUB16(n) (n >= BIT(16) ? (n >> 16) : n)
static int gpio_read(fdt_addr_t gpio_addr,
int gpio_bank, int gpio_pin)
{
uint32_t offset, bit;
bit = gpio_bank * 8 + gpio_pin;
offset = REG_PLUS4(GPIO_SWPORT_DDR, bit);
bit = BIT_SUB16(bit);
writel(WMSK_CLRBIT(bit), gpio_addr + offset);
return readl(gpio_addr + GPIO_EXT_PORT);
}
#else
#define GPIO_SWPORT_DDR 0x04
#define GPIO_EXT_PORT 0x50
static int gpio_read(fdt_addr_t gpio_addr,
int gpio_bank, int gpio_pin)
{
uint32_t val;
val = readl(gpio_addr + GPIO_SWPORT_DDR);
val &= ~(1 << (gpio_bank * 8 + gpio_pin));
writel(val, gpio_addr + GPIO_SWPORT_DDR);
return readl(gpio_addr + GPIO_EXT_PORT);
}
#endif
/* /*
* How to make it works ? * How to make it works ?
* *
@ -684,8 +721,7 @@ static int gpio_parse_base_address(fdt_addr_t *gpio_base_addr)
{ {
static int initialized; static int initialized;
ofnode parent, node; ofnode parent, node;
const char *name; int idx = 0;
int idx, nr = 0;
if (initialized) if (initialized)
return 0; return 0;
@ -698,23 +734,15 @@ static int gpio_parse_base_address(fdt_addr_t *gpio_base_addr)
ofnode_for_each_subnode(node, parent) { ofnode_for_each_subnode(node, parent) {
if (!ofnode_get_property(node, "gpio-controller", NULL)) { if (!ofnode_get_property(node, "gpio-controller", NULL)) {
debug(" - Can't find gpio-controller\n"); debug(" - Not gpio controller node\n");
continue; continue;
} }
name = ofnode_get_name(node);
if (!is_digit((char)*(name + 4))) {
debug(" - bad gpio node name: %s\n", name);
continue;
}
nr++;
idx = *(name + 4) - '0';
gpio_base_addr[idx] = ofnode_get_addr(node); gpio_base_addr[idx] = ofnode_get_addr(node);
debug(" - gpio%d: 0x%x\n", idx, (uint32_t)gpio_base_addr[idx]); debug(" - gpio%d: 0x%x\n", idx, (uint32_t)gpio_base_addr[idx]);
idx++;
} }
if (nr == 0) { if (idx == 0) {
debug(" - parse gpio address failed\n"); debug(" - parse gpio address failed\n");
return -EINVAL; return -EINVAL;
} }
@ -735,19 +763,19 @@ static int gpio_parse_base_address(fdt_addr_t *gpio_base_addr)
* eg: ...#gpio0a6=1#gpio1c2=0....dtb * eg: ...#gpio0a6=1#gpio1c2=0....dtb
* *
* 2. U-Boot dtsi about gpio node: * 2. U-Boot dtsi about gpio node:
* (1) enable "u-boot,dm-pre-reloc;" for all gpio node; * (1) enable "u-boot,dm-pre-reloc;" for [all] gpio node;
* (2) set all gpio status "disabled"(Because we just want their property); * (2) set all gpio status "disabled"(Because we just want their property);
*/ */
static int rockchip_read_dtb_by_gpio(const char *file_name) static int rockchip_read_dtb_by_gpio(const char *file_name)
{ {
static uint32_t cached_v[MAX_GPIO_NR]; static uint32_t cached_v[MAX_GPIO_NR];
fdt_addr_t gpio_base_addr[MAX_GPIO_NR]; static fdt_addr_t gpio_base_addr[MAX_GPIO_NR];
int ret, found = 0, offset = strlen(KEY_WORDS_GPIO); int ret, found = 0, offset = strlen(KEY_WORDS_GPIO);
uint8_t port, pin, bank, lvl, val; uint8_t port, pin, bank, lvl, val;
char *strgpio, *p; char *strgpio, *p;
uint32_t bit; uint32_t bit;
debug("%s\n", file_name); debug("[*] %s\n", file_name);
/* Parse gpio address */ /* Parse gpio address */
memset(gpio_base_addr, 0, sizeof(gpio_base_addr)); memset(gpio_base_addr, 0, sizeof(gpio_base_addr));
@ -787,25 +815,20 @@ static int rockchip_read_dtb_by_gpio(const char *file_name)
debug(" - can't find gpio%d base address\n", port); debug(" - can't find gpio%d base address\n", port);
return 0; return 0;
} }
cached_v[port] = gpio_read(gpio_base_addr[port], bank, pin);
/* Input mode */ debug(" - gpio-val[%d]: 0x%08x\n", port, cached_v[port]);
val = readl(gpio_base_addr[port] + GPIO_SWPORT_DDR);
val &= ~(1 << (bank * 8 + pin));
writel(val, gpio_base_addr[port] + GPIO_SWPORT_DDR);
cached_v[port] =
readl(gpio_base_addr[port] + GPIO_EXT_PORT);
} }
/* Verify result */ /* Verify result */
bit = bank * 8 + pin; bit = bank * 8 + pin;
val = cached_v[port] & (1 << bit) ? 1 : 0; val = cached_v[port] & (1 << bit) ? 1 : 0;
if (val == !!lvl) { if (val == !!lvl) {
found = 1; found = 1;
strgpio = strstr(p, KEY_WORDS_GPIO); strgpio = strstr(p, KEY_WORDS_GPIO);
} else { } else {
found = 0; found = 0;
debug(" - parse: gpio%d%c%d=%d, read=%d %s\n",
port, bank + 'a', pin, lvl, val, found ? "(Y)" : "(N)");
break; break;
} }
@ -813,6 +836,8 @@ static int rockchip_read_dtb_by_gpio(const char *file_name)
port, bank + 'a', pin, lvl, val, found ? "(Y)" : "(N)"); port, bank + 'a', pin, lvl, val, found ? "(Y)" : "(N)");
} }
debug(" # result: %s\n", found ? "OK" : "Try next one ..");
return found ? 0 : -ENOENT; return found ? 0 : -ENOENT;
} }