rockchip: clk: rv1108: Add some frequency setting interfaces
support PLL freq setting, support bus and peri clk freq setting, support aclk vio and dclk vop freq setting. Change-Id: I894552c1e1bb1bd13a143e200edf289234a53c1d Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
Kever Yang
parent
3b296e2b3d
commit
5cb579f13b
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@ -12,7 +12,11 @@
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (600 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define GPLL_HZ (1188 * 1000000)
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#define ACLK_PERI_HZ (148500000)
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#define HCLK_PERI_HZ (148500000)
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#define PCLK_PERI_HZ (74250000)
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#define ACLK_BUS_HZ (148500000)
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struct rv1108_clk_priv {
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struct rv1108_cru *cru;
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@ -110,6 +114,7 @@ enum {
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ACLK_BUS_PLL_SEL_DPLL = 2,
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ACLK_BUS_DIV_CON_SHIFT = 0,
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ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
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ACLK_BUS_DIV_CON_WIDTH = 5,
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/* CLKSEL_CON3 */
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PCLK_BUS_DIV_CON_SHIFT = 8,
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@ -139,6 +144,7 @@ enum {
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HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT,
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ACLK_PERI_DIV_CON_SHIFT = 0,
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ACLK_PERI_DIV_CON_MASK = 0x1f,
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PERI_DIV_CON_WIDTH = 5,
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/* CLKSEL24_CON */
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MAC_PLL_SEL_SHIFT = 12,
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@ -158,6 +164,38 @@ enum {
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SFC_CLK_DIV_SHIFT = 0,
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SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT,
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/* CLKSEL28_CON */
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ACLK_VIO1_PLL_SEL_SHIFT = 14,
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ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT,
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VIO_PLL_SEL_DPLL = 0,
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VIO_PLL_SEL_GPLL = 1,
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ACLK_VIO1_CLK_DIV_SHIFT = 8,
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ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH = 5,
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ACLK_VIO0_PLL_SEL_SHIFT = 6,
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ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT,
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ACLK_VIO0_CLK_DIV_SHIFT = 0,
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ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT,
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/* CLKSEL29_CON */
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PCLK_VIO_CLK_DIV_SHIFT = 8,
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PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT,
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HCLK_VIO_CLK_DIV_SHIFT = 0,
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HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT,
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/* CLKSEL32_CON */
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DCLK_VOP_SEL_SHIFT = 7,
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DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_HDMI = 0,
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DCLK_VOP_SEL_PLL = 1,
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DCLK_VOP_PLL_SEL_SHIFT = 6,
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DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT,
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DCLK_VOP_PLL_SEL_GPLL = 0,
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DCLK_VOP_PLL_SEL_DPLL = 1,
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DCLK_VOP_CLK_DIV_SHIFT = 0,
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DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT,
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DCLK_VOP_DIV_CON_WIDTH = 6,
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/* SOFTRST1_CON*/
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DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0,
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DDRPHY_SRSTN_CLKDIV_REQ = 1,
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@ -37,6 +37,9 @@ enum {
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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/* use integer mode */
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static inline int rv1108_pll_id(enum rk_clk_id clk_id)
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{
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@ -59,6 +62,58 @@ static inline int rv1108_pll_id(enum rk_clk_id clk_id)
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return id;
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}
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static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rv1108_pll_id(clk_id);
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struct rv1108_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/*
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* When power on or changing PLL setting,
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* we must force PLL into slow mode to ensure output stable clock.
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*/
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rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
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WORK_MODE_SLOW << WORK_MODE_SHIFT);
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/* use integer mode */
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rk_setreg(&pll->con3, 1 << DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
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rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);
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rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,
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(div->postdiv1 << POSTDIV1_SHIFT |
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div->postdiv2 << POSTDIV2_SHIFT |
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div->refdiv << REFDIV_SHIFT));
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rk_clrsetreg(&pll->con2, FRACDIV_MASK,
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(div->refdiv << REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT))
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udelay(1);
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/*
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* set PLL into normal mode.
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*/
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rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
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WORK_MODE_NORMAL << WORK_MODE_SHIFT);
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return 0;
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}
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static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
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enum rk_clk_id clk_id)
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{
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@ -76,7 +131,7 @@ static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
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fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
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postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
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postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
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refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT;
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refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK;
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freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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} else {
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freq = OSC_HZ;
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@ -156,6 +211,205 @@ static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
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return rv1108_saradc_get_clk(cru);
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}
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static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[28]);
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div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK,
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(src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) |
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(VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT));
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return rv1108_aclk_vio1_get_clk(cru);
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}
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static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[28]);
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div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,
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CLK_VIO_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK,
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(src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) |
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(VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT));
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/*HCLK_VIO default div = 4*/
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rk_clrsetreg(&cru->clksel_con[29],
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HCLK_VIO_CLK_DIV_MASK,
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3 << HCLK_VIO_CLK_DIV_SHIFT);
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/*PCLK_VIO default div = 4*/
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rk_clrsetreg(&cru->clksel_con[29],
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PCLK_VIO_CLK_DIV_MASK,
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3 << PCLK_VIO_CLK_DIV_SHIFT);
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return rv1108_aclk_vio0_get_clk(cru);
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}
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static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->clksel_con[32]);
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div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,
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DCLK_VOP_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
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assert(src_clk_div < 64);
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rk_clrsetreg(&cru->clksel_con[32],
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DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK |
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DCLK_VOP_SEL_SHIFT,
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(src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) |
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(DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) |
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(DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT));
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return rv1108_dclk_vop_get_clk(cru);
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}
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static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[2]);
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div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,
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ACLK_BUS_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[2],
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ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK,
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(src_clk_div << ACLK_BUS_DIV_CON_SHIFT) |
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(ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT));
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return rv1108_aclk_bus_get_clk(cru);
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}
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static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[23]);
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div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,
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PERI_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[23]);
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div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,
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PERI_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru)
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{
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u32 div, val;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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val = readl(&cru->clksel_con[23]);
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div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,
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PERI_DIV_CON_WIDTH);
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return DIV_TO_RATE(parent_rate, div);
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}
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static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[23],
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ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK,
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(src_clk_div << ACLK_PERI_DIV_CON_SHIFT) |
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(ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT));
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return rv1108_aclk_peri_get_clk(cru);
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}
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static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[23],
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HCLK_PERI_DIV_CON_MASK,
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(src_clk_div << HCLK_PERI_DIV_CON_SHIFT));
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return rv1108_hclk_peri_get_clk(cru);
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}
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static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
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{
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int src_clk_div;
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ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
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src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
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assert(src_clk_div < 32);
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rk_clrsetreg(&cru->clksel_con[23],
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PCLK_PERI_DIV_CON_MASK,
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(src_clk_div << PCLK_PERI_DIV_CON_SHIFT));
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return rv1108_pclk_peri_get_clk(cru);
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}
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static ulong rv1108_clk_get_rate(struct clk *clk)
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{
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struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
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@ -165,6 +419,20 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
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return rkclk_pll_get_rate(priv->cru, clk->id);
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case SCLK_SARADC:
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return rv1108_saradc_get_clk(priv->cru);
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case ACLK_VIO0:
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return rv1108_aclk_vio0_get_clk(priv->cru);
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case ACLK_VIO1:
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return rv1108_aclk_vio1_get_clk(priv->cru);
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case DCLK_VOP:
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return rv1108_dclk_vop_get_clk(priv->cru);
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case ACLK_PRE:
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return rv1108_aclk_bus_get_clk(priv->cru);
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case ACLK_PERI:
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return rv1108_aclk_peri_get_clk(priv->cru);
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case HCLK_PERI:
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return rv1108_hclk_peri_get_clk(priv->cru);
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case PCLK_PERI:
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return rv1108_pclk_peri_get_clk(priv->cru);
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default:
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return -ENOENT;
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}
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@ -185,6 +453,27 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
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case SCLK_SARADC:
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new_rate = rv1108_saradc_set_clk(priv->cru, rate);
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break;
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case ACLK_VIO0:
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new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate);
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break;
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case ACLK_VIO1:
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new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate);
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break;
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case DCLK_VOP:
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new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate);
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break;
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case ACLK_PRE:
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new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case ACLK_PERI:
|
||||
new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case HCLK_PERI:
|
||||
new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate);
|
||||
break;
|
||||
case PCLK_PERI:
|
||||
new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate);
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
|
@ -199,14 +488,34 @@ static const struct clk_ops rv1108_clk_ops = {
|
|||
|
||||
static void rkclk_init(struct rv1108_cru *cru)
|
||||
{
|
||||
unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM);
|
||||
unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR);
|
||||
unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
unsigned int apll, dpll, gpll;
|
||||
unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri;
|
||||
|
||||
aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2);
|
||||
aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2);
|
||||
hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2);
|
||||
pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2);
|
||||
rv1108_aclk_vio0_set_clk(cru, 297000000);
|
||||
rv1108_aclk_vio1_set_clk(cru, 297000000);
|
||||
|
||||
/* configure apll */
|
||||
rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
|
||||
rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
|
||||
aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ);
|
||||
aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ);
|
||||
hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ);
|
||||
pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ);
|
||||
|
||||
apll = rkclk_pll_get_rate(cru, CLK_ARM);
|
||||
dpll = rkclk_pll_get_rate(cru, CLK_DDR);
|
||||
gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
|
||||
|
||||
rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
|
||||
0 << MAC_CLK_DIV_SHIFT);
|
||||
|
||||
printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
|
||||
printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n",
|
||||
aclk_bus, aclk_peri, hclk_peri, pclk_peri);
|
||||
}
|
||||
|
||||
static int rv1108_clk_probe(struct udevice *dev)
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define SCLK_MACREF_OUT 90
|
||||
#define SCLK_SARADC 91
|
||||
|
||||
#define DCLK_VOP 187
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 192
|
||||
|
|
@ -48,7 +49,9 @@
|
|||
#define ACLK_CORE 194
|
||||
#define ACLK_ENMCORE 195
|
||||
#define ACLK_GMAC 196
|
||||
|
||||
#define ACLK_VIO0 200
|
||||
#define ACLK_VIO1 201
|
||||
#define ACLK_PERI 209
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO1 256
|
||||
|
|
@ -69,6 +72,7 @@
|
|||
#define PCLK_PERI 271
|
||||
#define PCLK_GMAC 272
|
||||
#define PCLK_SARADC 273
|
||||
#define PCLK_VIO 276
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 320
|
||||
|
|
@ -80,8 +84,9 @@
|
|||
#define HCLK_EMMC 326
|
||||
#define HCLK_PERI 327
|
||||
#define HCLK_SFC 328
|
||||
#define HCLK_VIO 332
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_SFC + 1)
|
||||
#define CLK_NR_CLKS (HCLK_VIO + 1)
|
||||
|
||||
/* reset id */
|
||||
#define SRST_CORE_PO_AD 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue