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common: spl: support enable D-cache for 32-bit platform 

- Initial gd->bd->bi_dram[] for arm32.
- Add a configure to enable/disable SPL D-cache.
- Please make sure CONFIG_SPL_SYS_MALLOC_F_LEN is large
  enough for TLB and bd_t buffer while enabling dcache

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I85f2169fe44b44e16edb15a9538df516037e9823
This commit is contained in:
Joseph Chen 2020-03-18 18:31:46 +08:00
parent c155446281
commit 594e14a437
2 changed files with 52 additions and 9 deletions
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7
Kconfig
View File

@ -321,6 +321,13 @@ config SPL_FIT_HW_CRYPTO
help help
Enable SPL hardware crypto for FIT image checksum and rsa verify. Enable SPL hardware crypto for FIT image checksum and rsa verify.
config SPL_SYS_DCACHE_OFF
bool "Disable SPL dcache"
default y
help
Disable SPL dcache. Please make sure CONFIG_SPL_SYS_MALLOC_F_LEN
is large enough to malloc TLB and bd_t buffer while enabling dcache.
endif # SPL endif # SPL
endif # FIT endif # FIT

54
common/spl/spl.c
View File

@ -221,6 +221,45 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
image_entry(); image_entry();
} }
/*
* 64-bit: No special operation.
*
* 32-bit: Initial gd->bd->bi_dram[] to active dcache attr of memory.
* Assuming 256MB is enough for SPL(MMU still maps 4GB size).
*/
#ifndef CONFIG_SPL_SYS_DCACHE_OFF
static int spl_dcache_enable(void)
{
bool free_bd = false;
#ifndef CONFIG_ARM64
if (!gd->bd) {
gd->bd = calloc(1, sizeof(bd_t));
if (!gd->bd) {
debug("spl: no bd_t memory\n");
return -ENOMEM;
}
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = SZ_256M;
free_bd = true;
}
#endif
/* TLB memory should be 64KB base align and 4KB end align */
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (ulong)memalign(SZ_64K, ALIGN(PGTABLE_SIZE, SZ_4K));
if (!gd->arch.tlb_addr) {
debug("spl: no TLB memory\n");
return -ENOMEM;
}
dcache_enable();
if (free_bd)
free(gd->bd);
return 0;
}
#endif
static int spl_common_init(bool setup_malloc) static int spl_common_init(bool setup_malloc)
{ {
int ret; int ret;
@ -241,16 +280,13 @@ static int spl_common_init(bool setup_malloc)
* setup D-cache as early as possible after malloc setup * setup D-cache as early as possible after malloc setup
* I-cache has been setup at early assembly code by default. * I-cache has been setup at early assembly code by default.
*/ */
#if !defined(CONFIG_TPL_BUILD) #ifndef CONFIG_SPL_SYS_DCACHE_OFF
/* tlb memory should be 64KB align for base and 4KB align for end */ ret = spl_dcache_enable();
gd->arch.tlb_size = PGTABLE_SIZE; if (ret) {
gd->arch.tlb_addr = (ulong)memalign(SZ_64K, ALIGN(PGTABLE_SIZE, SZ_4K)); debug("spl_dcache_enable() return error %d\n", ret);
if (gd->arch.tlb_addr) return ret;
dcache_enable(); }
else
debug("spl: no tlb memory\n");
#endif #endif
ret = bootstage_init(true); ret = bootstage_init(true);
if (ret) { if (ret) {
debug("%s: Failed to set up bootstage: ret=%d\n", __func__, debug("%s: Failed to set up bootstage: ret=%d\n", __func__,