rockchip: dts: rv1126/1109: sync from kernel
sync from: a96b35a clk: rockchip: rv1126: Add support for otp Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I12db524cf784479de567515f47da99df611a48ad
This commit is contained in:
Joseph Chen
parent
7ebda5c0cb
commit
593e1e6d64
|
|
@ -0,0 +1,266 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
&pinctrl {
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
|
||||
bias-pull-up;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
|
||||
bias-pull-up;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
|
||||
bias-pull-up;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
|
||||
bias-pull-up;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
|
||||
bias-pull-up;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
|
||||
bias-pull-up;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
|
||||
bias-pull-up;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
|
||||
bias-pull-up;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
|
||||
bias-pull-up;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
|
||||
bias-pull-up;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
|
||||
bias-pull-down;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_1: pcfg-pull-up-drv-level-1 {
|
||||
bias-pull-up;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_2: pcfg-pull-up-drv-level-2 {
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_3: pcfg-pull-up-drv-level-3 {
|
||||
bias-pull-up;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_4: pcfg-pull-up-drv-level-4 {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_5: pcfg-pull-up-drv-level-5 {
|
||||
bias-pull-up;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_6: pcfg-pull-up-drv-level-6 {
|
||||
bias-pull-up;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_7: pcfg-pull-up-drv-level-7 {
|
||||
bias-pull-up;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_8: pcfg-pull-up-drv-level-8 {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_9: pcfg-pull-up-drv-level-9 {
|
||||
bias-pull-up;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_10: pcfg-pull-up-drv-level-10 {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_11: pcfg-pull-up-drv-level-11 {
|
||||
bias-pull-up;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_12: pcfg-pull-up-drv-level-12 {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_13: pcfg-pull-up-drv-level-13 {
|
||||
bias-pull-up;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_14: pcfg-pull-up-drv-level-14 {
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
pcfg_pull_down_drv_level_15: pcfg-pull-up-drv-level-15 {
|
||||
bias-pull-up;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_smt: pcfg-pull-up-smt {
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
pcfg_pull_down_smt: pcfg-pull-down-smt {
|
||||
bias-pull-down;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rv1109-evb-v10.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RV1109 EVB DDR3 Board";
|
||||
compatible = "rockchip,rv1109-evb-ddr3-v10", "rockchip,rv1109";
|
||||
|
||||
chosen {
|
||||
bootargs = "clk_ignore_unused earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rv1109.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RV1109 EVB Board";
|
||||
compatible = "rockchip,rv1109-evb-v10", "rockchip,rv1109";
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
mmc-hs200-1_8v;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
supports-emmc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fiq_debugger {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
snps,reset-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
assigned-clocks = <&cru CLK_GMAC_SRC>;
|
||||
assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>;
|
||||
assigned-clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
tx_delay = <0x40>;
|
||||
rx_delay = <0x3a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
supports-sd;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
sd-uhs-sdr104;
|
||||
supports-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rv1126.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rv1109";
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@f02;
|
||||
/delete-node/ cpu@f03;
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
#include <dt-bindings/memory/rv1126-dram.h>
|
||||
|
||||
/ {
|
||||
ddr_timing: ddr_timing {
|
||||
compatible = "rockchip,ddr-timing";
|
||||
ddr2_speed_bin = <DDR2_DEFAULT>;
|
||||
ddr3_speed_bin = <DDR3_DEFAULT>;
|
||||
ddr4_speed_bin = <DDR4_DEFAULT>;
|
||||
pd_idle = <0>;
|
||||
sr_idle = <0>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
|
||||
auto_pd_dis_freq = <1066>;
|
||||
auto_sr_dis_freq = <800>;
|
||||
ddr2_dll_dis_freq = <300>;
|
||||
ddr3_dll_dis_freq = <300>;
|
||||
ddr4_dll_dis_freq = <625>;
|
||||
phy_dll_dis_freq = <400>;
|
||||
|
||||
ddr2_odt_dis_freq = <100>;
|
||||
phy_ddr2_odt_dis_freq = <100>;
|
||||
ddr2_drv = <DDR2_DS_REDUCE>;
|
||||
ddr2_odt = <DDR2_ODT_150ohm>;
|
||||
phy_ddr2_ca_drv = <PHY_DDR3_RON_34ohm>;
|
||||
phy_ddr2_ck_drv = <PHY_DDR3_RON_42ohm>;
|
||||
phy_ddr2_dq_drv = <PHY_DDR3_RON_34ohm>;
|
||||
phy_ddr2_odt = <PHY_DDR3_RTT_241ohm>;
|
||||
|
||||
ddr3_odt_dis_freq = <400>;
|
||||
phy_ddr3_odt_dis_freq = <400>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
phy_ddr3_ca_drv = <PHY_DDR3_RON_34ohm>;
|
||||
phy_ddr3_ck_drv = <PHY_DDR3_RON_42ohm>;
|
||||
phy_ddr3_dq_drv = <PHY_DDR3_RON_34ohm>;
|
||||
phy_ddr3_odt = <PHY_DDR3_RTT_241ohm>;
|
||||
|
||||
phy_lpddr2_odt_dis_freq = <666>;
|
||||
lpddr2_drv = <LP2_DS_40ohm>;
|
||||
phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR3_RON_34ohm>;
|
||||
phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR3_RON_41ohm>;
|
||||
phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR3_RON_34ohm>;
|
||||
phy_lpddr2_odt = <PHY_DDR4_LPDDR3_RTT_DISABLE>;
|
||||
|
||||
lpddr3_odt_dis_freq = <400>;
|
||||
phy_lpddr3_odt_dis_freq = <400>;
|
||||
lpddr3_drv = <LP3_DS_40ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_34ohm>;
|
||||
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_41ohm>;
|
||||
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_34ohm>;
|
||||
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RTT_247ohm>;
|
||||
|
||||
lpddr4_odt_dis_freq = <800>;
|
||||
phy_lpddr4_odt_dis_freq = <800>;
|
||||
lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
phy_lpddr4_ca_drv = <PHY_LPDDR4_RON_34ohm>;
|
||||
phy_lpddr4_ck_cs_drv = <PHY_LPDDR4_RON_43ohm>;
|
||||
phy_lpddr4_dq_drv = <PHY_LPDDR4_RON_34ohm>;
|
||||
phy_lpddr4_odt = <PHY_LPDDR4_RTT_253ohm>;
|
||||
|
||||
ddr4_odt_dis_freq = <666>;
|
||||
phy_ddr4_odt_dis_freq = <666>;
|
||||
ddr4_drv = <DDR4_DS_34ohm>;
|
||||
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
|
||||
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_34ohm>;
|
||||
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_41ohm>;
|
||||
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_34ohm>;
|
||||
phy_ddr4_odt = <PHY_DDR4_LPDDR3_RTT_247ohm>;
|
||||
|
||||
/*
|
||||
* CA de-skew, one step is 20ps, range 0-63
|
||||
* name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew
|
||||
*/
|
||||
a0_a3_a3_cke1-a_de-skew = <7>;
|
||||
a1_ba1_null_cke0-b_de-skew = <7>;
|
||||
a2_a9_a9_a4-a_de-skew = <7>;
|
||||
a3_a15_null_a5-b_de-skew = <7>;
|
||||
a4_a6_a6_ck-a_de-skew = <7>;
|
||||
a5_a12_null_odt0-b_de-skew = <7>;
|
||||
a6_ba2_null_a0-a_de-skew = <7>;
|
||||
a7_a4_a4_odt0-a_de-skew = <7>;
|
||||
a8_a1_a1_cke0-a_de-skew = <7>;
|
||||
a9_a5_a5_a5-a_de-skew = <7>;
|
||||
a10_a8_a8_clkb-a_de-skew = <7>;
|
||||
a11_a7_a7_ca2-a_de-skew = <7>;
|
||||
a12_rasn_null_ca1-a_de-skew = <7>;
|
||||
a13_a13_null_ca3-a_de-skew = <7>;
|
||||
a14_a14_null_csb1-b_de-skew = <7>;
|
||||
a15_a10_null_ca0-b_de-skew = <7>;
|
||||
a16_a11_null_csb0-b_de-skew = <7>;
|
||||
a17_null_null_null_de-skew = <7>;
|
||||
ba0_csb1_csb1_csb0-a_de-skew = <7>;
|
||||
ba1_wen_null_cke1-b_de-skew = <7>;
|
||||
bg0_odt1_odt1_csb1-a_de-skew = <7>;
|
||||
bg1_a2_a2_odt1-a_de-skew = <7>;
|
||||
cke0_casb_null_ca1-b_de-skew = <7>;
|
||||
ck_ck_ck_ck-b_de-skew = <7>;
|
||||
ckb_ckb_ckb_ckb-b_de-skew = <7>;
|
||||
csb0_odt0_odt0_ca2-b_de-skew = <7>;
|
||||
odt0_csb0_csb0_ca4-b_de-skew = <7>;
|
||||
resetn_resetn_null-resetn_de-skew = <7>;
|
||||
actn_cke_cke_ca3-b_de-skew = <7>;
|
||||
cke1_null_null_null_de-skew = <7>;
|
||||
csb1_ba0_null_null_de-skew = <7>;
|
||||
odt1_a0_a0_odt1-b_de-skew = <7>;
|
||||
|
||||
/* DATA de-skew, one step is 20ps, range 0-63 */
|
||||
/* cs0_skew_a */
|
||||
cs0_dm0_rx_de-skew = <7>;
|
||||
cs0_dq0_rx_de-skew = <7>;
|
||||
cs0_dq1_rx_de-skew = <7>;
|
||||
cs0_dq2_rx_de-skew = <7>;
|
||||
cs0_dq3_rx_de-skew = <7>;
|
||||
cs0_dq4_rx_de-skew = <7>;
|
||||
cs0_dq5_rx_de-skew = <7>;
|
||||
cs0_dq6_rx_de-skew = <7>;
|
||||
cs0_dq7_rx_de-skew = <7>;
|
||||
cs0_dqs0p_rx_de-skew = <14>;
|
||||
cs0_dqs0n_rx_de-skew = <14>;
|
||||
cs0_dm1_rx_de-skew = <7>;
|
||||
cs0_dq8_rx_de-skew = <7>;
|
||||
cs0_dq9_rx_de-skew = <7>;
|
||||
cs0_dq10_rx_de-skew = <7>;
|
||||
cs0_dq11_rx_de-skew = <7>;
|
||||
cs0_dq12_rx_de-skew = <7>;
|
||||
cs0_dq13_rx_de-skew = <7>;
|
||||
cs0_dq14_rx_de-skew = <7>;
|
||||
cs0_dq15_rx_de-skew = <7>;
|
||||
cs0_dqs1p_rx_de-skew = <14>;
|
||||
cs0_dqs1n_rx_de-skew = <14>;
|
||||
cs0_dm0_tx_de-skew = <7>;
|
||||
cs0_dq0_tx_de-skew = <7>;
|
||||
cs0_dq1_tx_de-skew = <7>;
|
||||
cs0_dq2_tx_de-skew = <7>;
|
||||
cs0_dq3_tx_de-skew = <7>;
|
||||
cs0_dq4_tx_de-skew = <7>;
|
||||
cs0_dq5_tx_de-skew = <7>;
|
||||
cs0_dq6_tx_de-skew = <7>;
|
||||
cs0_dq7_tx_de-skew = <7>;
|
||||
cs0_dqs0p_tx_de-skew = <7>;
|
||||
cs0_dqs0n_tx_de-skew = <7>;
|
||||
cs0_dm1_tx_de-skew = <7>;
|
||||
cs0_dq8_tx_de-skew = <7>;
|
||||
cs0_dq9_tx_de-skew = <7>;
|
||||
cs0_dq10_tx_de-skew = <7>;
|
||||
cs0_dq11_tx_de-skew = <7>;
|
||||
cs0_dq12_tx_de-skew = <7>;
|
||||
cs0_dq13_tx_de-skew = <7>;
|
||||
cs0_dq14_tx_de-skew = <7>;
|
||||
cs0_dq15_tx_de-skew = <7>;
|
||||
cs0_dqs1p_tx_de-skew = <7>;
|
||||
cs0_dqs1n_tx_de-skew = <7>;
|
||||
|
||||
/* cs0_skew_b */
|
||||
cs0_dm2_rx_de-skew = <7>;
|
||||
cs0_dq16_rx_de-skew = <7>;
|
||||
cs0_dq17_rx_de-skew = <7>;
|
||||
cs0_dq18_rx_de-skew = <7>;
|
||||
cs0_dq19_rx_de-skew = <7>;
|
||||
cs0_dq20_rx_de-skew = <7>;
|
||||
cs0_dq21_rx_de-skew = <7>;
|
||||
cs0_dq22_rx_de-skew = <7>;
|
||||
cs0_dq23_rx_de-skew = <7>;
|
||||
cs0_dqs2p_rx_de-skew = <14>;
|
||||
cs0_dqs2n_rx_de-skew = <14>;
|
||||
cs0_dm3_rx_de-skew = <7>;
|
||||
cs0_dq24_rx_de-skew = <7>;
|
||||
cs0_dq25_rx_de-skew = <7>;
|
||||
cs0_dq26_rx_de-skew = <7>;
|
||||
cs0_dq27_rx_de-skew = <7>;
|
||||
cs0_dq28_rx_de-skew = <7>;
|
||||
cs0_dq29_rx_de-skew = <7>;
|
||||
cs0_dq30_rx_de-skew = <7>;
|
||||
cs0_dq31_rx_de-skew = <7>;
|
||||
cs0_dqs3p_rx_de-skew = <14>;
|
||||
cs0_dqs3n_rx_de-skew = <14>;
|
||||
cs0_dm2_tx_de-skew = <7>;
|
||||
cs0_dq16_tx_de-skew = <7>;
|
||||
cs0_dq17_tx_de-skew = <7>;
|
||||
cs0_dq18_tx_de-skew = <7>;
|
||||
cs0_dq19_tx_de-skew = <7>;
|
||||
cs0_dq20_tx_de-skew = <7>;
|
||||
cs0_dq21_tx_de-skew = <7>;
|
||||
cs0_dq22_tx_de-skew = <7>;
|
||||
cs0_dq23_tx_de-skew = <7>;
|
||||
cs0_dqs2p_tx_de-skew = <7>;
|
||||
cs0_dqs2n_tx_de-skew = <7>;
|
||||
cs0_dm3_tx_de-skew = <7>;
|
||||
cs0_dq24_tx_de-skew = <7>;
|
||||
cs0_dq25_tx_de-skew = <7>;
|
||||
cs0_dq26_tx_de-skew = <7>;
|
||||
cs0_dq27_tx_de-skew = <7>;
|
||||
cs0_dq28_tx_de-skew = <7>;
|
||||
cs0_dq29_tx_de-skew = <7>;
|
||||
cs0_dq30_tx_de-skew = <7>;
|
||||
cs0_dq31_tx_de-skew = <7>;
|
||||
cs0_dqs3p_tx_de-skew = <7>;
|
||||
cs0_dqs3n_tx_de-skew = <7>;
|
||||
|
||||
/* cs1_skew_a */
|
||||
cs1_dm0_rx_de-skew = <7>;
|
||||
cs1_dq0_rx_de-skew = <7>;
|
||||
cs1_dq1_rx_de-skew = <7>;
|
||||
cs1_dq2_rx_de-skew = <7>;
|
||||
cs1_dq3_rx_de-skew = <7>;
|
||||
cs1_dq4_rx_de-skew = <7>;
|
||||
cs1_dq5_rx_de-skew = <7>;
|
||||
cs1_dq6_rx_de-skew = <7>;
|
||||
cs1_dq7_rx_de-skew = <7>;
|
||||
cs1_dqs0p_rx_de-skew = <14>;
|
||||
cs1_dqs0n_rx_de-skew = <14>;
|
||||
cs1_dm1_rx_de-skew = <7>;
|
||||
cs1_dq8_rx_de-skew = <7>;
|
||||
cs1_dq9_rx_de-skew = <7>;
|
||||
cs1_dq10_rx_de-skew = <7>;
|
||||
cs1_dq11_rx_de-skew = <7>;
|
||||
cs1_dq12_rx_de-skew = <7>;
|
||||
cs1_dq13_rx_de-skew = <7>;
|
||||
cs1_dq14_rx_de-skew = <7>;
|
||||
cs1_dq15_rx_de-skew = <7>;
|
||||
cs1_dqs1p_rx_de-skew = <14>;
|
||||
cs1_dqs1n_rx_de-skew = <14>;
|
||||
cs1_dm0_tx_de-skew = <7>;
|
||||
cs1_dq0_tx_de-skew = <7>;
|
||||
cs1_dq1_tx_de-skew = <7>;
|
||||
cs1_dq2_tx_de-skew = <7>;
|
||||
cs1_dq3_tx_de-skew = <7>;
|
||||
cs1_dq4_tx_de-skew = <7>;
|
||||
cs1_dq5_tx_de-skew = <7>;
|
||||
cs1_dq6_tx_de-skew = <7>;
|
||||
cs1_dq7_tx_de-skew = <7>;
|
||||
cs1_dqs0p_tx_de-skew = <7>;
|
||||
cs1_dqs0n_tx_de-skew = <7>;
|
||||
cs1_dm1_tx_de-skew = <7>;
|
||||
cs1_dq8_tx_de-skew = <7>;
|
||||
cs1_dq9_tx_de-skew = <7>;
|
||||
cs1_dq10_tx_de-skew = <7>;
|
||||
cs1_dq11_tx_de-skew = <7>;
|
||||
cs1_dq12_tx_de-skew = <7>;
|
||||
cs1_dq13_tx_de-skew = <7>;
|
||||
cs1_dq14_tx_de-skew = <7>;
|
||||
cs1_dq15_tx_de-skew = <7>;
|
||||
cs1_dqs1p_tx_de-skew = <7>;
|
||||
cs1_dqs1n_tx_de-skew = <7>;
|
||||
|
||||
/* cs1_skew_b */
|
||||
cs1_dm2_rx_de-skew = <7>;
|
||||
cs1_dq16_rx_de-skew = <7>;
|
||||
cs1_dq17_rx_de-skew = <7>;
|
||||
cs1_dq18_rx_de-skew = <7>;
|
||||
cs1_dq19_rx_de-skew = <7>;
|
||||
cs1_dq20_rx_de-skew = <7>;
|
||||
cs1_dq21_rx_de-skew = <7>;
|
||||
cs1_dq22_rx_de-skew = <7>;
|
||||
cs1_dq23_rx_de-skew = <7>;
|
||||
cs1_dqs2p_rx_de-skew = <14>;
|
||||
cs1_dqs2n_rx_de-skew = <14>;
|
||||
cs1_dm3_rx_de-skew = <7>;
|
||||
cs1_dq24_rx_de-skew = <7>;
|
||||
cs1_dq25_rx_de-skew = <7>;
|
||||
cs1_dq26_rx_de-skew = <7>;
|
||||
cs1_dq27_rx_de-skew = <7>;
|
||||
cs1_dq28_rx_de-skew = <7>;
|
||||
cs1_dq29_rx_de-skew = <7>;
|
||||
cs1_dq30_rx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
|
||||
cs1_dqs3p_rx_de-skew = <14>;
|
||||
cs1_dqs3n_rx_de-skew = <14>;
|
||||
cs1_dm2_tx_de-skew = <7>;
|
||||
cs1_dq16_tx_de-skew = <7>;
|
||||
cs1_dq17_tx_de-skew = <7>;
|
||||
cs1_dq18_tx_de-skew = <7>;
|
||||
cs1_dq19_tx_de-skew = <7>;
|
||||
cs1_dq20_tx_de-skew = <7>;
|
||||
cs1_dq21_tx_de-skew = <7>;
|
||||
cs1_dq22_tx_de-skew = <7>;
|
||||
cs1_dq23_tx_de-skew = <7>;
|
||||
cs1_dqs2p_tx_de-skew = <7>;
|
||||
cs1_dqs2n_tx_de-skew = <7>;
|
||||
cs1_dm3_tx_de-skew = <7>;
|
||||
cs1_dq24_tx_de-skew = <7>;
|
||||
cs1_dq25_tx_de-skew = <7>;
|
||||
cs1_dq26_tx_de-skew = <7>;
|
||||
cs1_dq27_tx_de-skew = <7>;
|
||||
cs1_dq28_tx_de-skew = <7>;
|
||||
cs1_dq29_tx_de-skew = <7>;
|
||||
cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_tx_de-skew = <7>;
|
||||
cs1_dqs3p_tx_de-skew = <7>;
|
||||
cs1_dqs3n_tx_de-skew = <7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -10,6 +10,12 @@
|
|||
/ {
|
||||
model = "Rockchip RV1126 Evaluation Board";
|
||||
compatible = "rockchip,rv1126-evb", "rockchip,rv1126";
|
||||
|
||||
ramdisk-ro {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "ramdisk-ro";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,15 +1,45 @@
|
|||
/*
|
||||
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
|
||||
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &emmc;
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
clock-frequency = <24000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pmu {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pmugrf {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pmucru {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&cru {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -17,8 +47,3 @@
|
|||
&grf {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2017 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
|
||||
#define DDR2_DEFAULT (0)
|
||||
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
|
||||
#define DDR4_1600J (0) /* 10-10-10 */
|
||||
#define DDR4_1600K (1) /* 11-11-11 */
|
||||
#define DDR4_1600L (2) /* 12-12-12 */
|
||||
#define DDR4_1866L (3) /* 12-12-12 */
|
||||
#define DDR4_1866M (4) /* 13-13-13 */
|
||||
#define DDR4_1866N (5) /* 14-14-14 */
|
||||
#define DDR4_2133N (6) /* 14-14-14 */
|
||||
#define DDR4_2133P (7) /* 15-15-15 */
|
||||
#define DDR4_2133R (8) /* 16-16-16 */
|
||||
#define DDR4_2400P (9) /* 15-15-15 */
|
||||
#define DDR4_2400R (10) /* 16-16-16 */
|
||||
#define DDR4_2400U (11) /* 18-18-18 */
|
||||
#define DDR4_DEFAULT (12)
|
||||
|
||||
#define PAUSE_CPU_STACK_SIZE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -210,6 +210,8 @@
|
|||
#define CLK_CORE_NPU 144
|
||||
#define CLK_CORE_NPUPVTM 145
|
||||
#define CLK_NPUPVTM 146
|
||||
#define SCLK_DDRCLK 147
|
||||
#define CLK_OTP 148
|
||||
|
||||
/* dclk */
|
||||
#define DCLK_DECOM 150
|
||||
|
|
@ -350,8 +352,9 @@
|
|||
#define PCLK_CSIPHY1 291
|
||||
#define PCLK_USBPHY_HOST 292
|
||||
#define PCLK_USBPHY_OTG 293
|
||||
#define PCLK_OTP 294
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_USBPHY_OTG + 1)
|
||||
#define CLK_NR_CLKS (PCLK_OTP + 1)
|
||||
|
||||
/* pmu soft-reset indices */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,231 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H
|
||||
#define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H
|
||||
|
||||
#define DDR2_DS_FULL (0)
|
||||
#define DDR2_DS_REDUCE (1)
|
||||
|
||||
#define DDR2_ODT_DIS (0)
|
||||
#define DDR2_ODT_50ohm (50) /* optional */
|
||||
#define DDR2_ODT_75ohm (75)
|
||||
#define DDR2_ODT_150ohm (150)
|
||||
|
||||
#define DDR3_DS_34ohm (34)
|
||||
#define DDR3_DS_40ohm (40)
|
||||
|
||||
#define DDR3_ODT_DIS (0)
|
||||
#define DDR3_ODT_40ohm (40)
|
||||
#define DDR3_ODT_60ohm (60)
|
||||
#define DDR3_ODT_120ohm (120)
|
||||
|
||||
#define LP2_DS_34ohm (34)
|
||||
#define LP2_DS_40ohm (40)
|
||||
#define LP2_DS_48ohm (48)
|
||||
#define LP2_DS_60ohm (60)
|
||||
#define LP2_DS_68_6ohm (68) /* optional */
|
||||
#define LP2_DS_80ohm (80)
|
||||
#define LP2_DS_120ohm (120) /* optional */
|
||||
|
||||
#define LP3_DS_34ohm (34)
|
||||
#define LP3_DS_40ohm (40)
|
||||
#define LP3_DS_48ohm (48)
|
||||
#define LP3_DS_60ohm (60)
|
||||
#define LP3_DS_80ohm (80)
|
||||
#define LP3_DS_34D_40U (3440)
|
||||
#define LP3_DS_40D_48U (4048)
|
||||
#define LP3_DS_34D_48U (3448)
|
||||
|
||||
#define LP3_ODT_DIS (0)
|
||||
#define LP3_ODT_60ohm (60)
|
||||
#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
|
||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_DISABLE (0)
|
||||
#define PHY_DDR3_RON_506ohm (1)
|
||||
#define PHY_DDR3_RON_253ohm (2)
|
||||
#define PHY_DDR3_RON_169hm (3)
|
||||
#define PHY_DDR3_RON_127ohm (4)
|
||||
#define PHY_DDR3_RON_101ohm (5)
|
||||
#define PHY_DDR3_RON_84ohm (6)
|
||||
#define PHY_DDR3_RON_72ohm (7)
|
||||
#define PHY_DDR3_RON_63ohm (16)
|
||||
#define PHY_DDR3_RON_56ohm (17)
|
||||
#define PHY_DDR3_RON_51ohm (18)
|
||||
#define PHY_DDR3_RON_46ohm (19)
|
||||
#define PHY_DDR3_RON_42ohm (20)
|
||||
#define PHY_DDR3_RON_39ohm (21)
|
||||
#define PHY_DDR3_RON_36ohm (22)
|
||||
#define PHY_DDR3_RON_34ohm (23)
|
||||
#define PHY_DDR3_RON_32ohm (24)
|
||||
#define PHY_DDR3_RON_30ohm (25)
|
||||
#define PHY_DDR3_RON_28ohm (26)
|
||||
#define PHY_DDR3_RON_27ohm (27)
|
||||
#define PHY_DDR3_RON_25ohm (28)
|
||||
#define PHY_DDR3_RON_24ohm (29)
|
||||
#define PHY_DDR3_RON_23ohm (30)
|
||||
#define PHY_DDR3_RON_22ohm (31)
|
||||
|
||||
#define PHY_DDR3_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RTT_953ohm (1)
|
||||
#define PHY_DDR3_RTT_483ohm (2)
|
||||
#define PHY_DDR3_RTT_320ohm (3)
|
||||
#define PHY_DDR3_RTT_241ohm (4)
|
||||
#define PHY_DDR3_RTT_193ohm (5)
|
||||
#define PHY_DDR3_RTT_161ohm (6)
|
||||
#define PHY_DDR3_RTT_138ohm (7)
|
||||
#define PHY_DDR3_RTT_121ohm (16)
|
||||
#define PHY_DDR3_RTT_107ohm (17)
|
||||
#define PHY_DDR3_RTT_97ohm (18)
|
||||
#define PHY_DDR3_RTT_88ohm (19)
|
||||
#define PHY_DDR3_RTT_80ohm (20)
|
||||
#define PHY_DDR3_RTT_74ohm (21)
|
||||
#define PHY_DDR3_RTT_69ohm (22)
|
||||
#define PHY_DDR3_RTT_64ohm (23)
|
||||
#define PHY_DDR3_RTT_60ohm (24)
|
||||
#define PHY_DDR3_RTT_57ohm (25)
|
||||
#define PHY_DDR3_RTT_54ohm (26)
|
||||
#define PHY_DDR3_RTT_51ohm (27)
|
||||
#define PHY_DDR3_RTT_48ohm (28)
|
||||
#define PHY_DDR3_RTT_46ohm (29)
|
||||
#define PHY_DDR3_RTT_44ohm (30)
|
||||
#define PHY_DDR3_RTT_42ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_570ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_285ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_190ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_142ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_114ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_95ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_81ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_71ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_63ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_57ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_52ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_47ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_44ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_41ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_38ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_36ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_34ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_32ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_30ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_28ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_27ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_26ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_25ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RTT_973ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RTT_493ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RTT_327ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RTT_247ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RTT_197ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RTT_164ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RTT_141ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RTT_123ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RTT_109ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RTT_99ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RTT_90ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RTT_82ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RTT_76ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RTT_70ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RTT_66ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RTT_62ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RTT_58ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RTT_55ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RTT_52ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RTT_49ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RTT_47ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RTT_45ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RTT_43ohm (31)
|
||||
|
||||
#define PHY_LPDDR4_RON_DISABLE (0)
|
||||
#define PHY_LPDDR4_RON_606ohm (1)
|
||||
#define PHY_LPDDR4_RON_303ohm (2)
|
||||
#define PHY_LPDDR4_RON_202ohm (3)
|
||||
#define PHY_LPDDR4_RON_152ohm (4)
|
||||
#define PHY_LPDDR4_RON_121ohm (5)
|
||||
#define PHY_LPDDR4_RON_101ohm (6)
|
||||
#define PHY_LPDDR4_RON_87ohm (7)
|
||||
#define PHY_LPDDR4_RON_76ohm (16)
|
||||
#define PHY_LPDDR4_RON_67ohm (17)
|
||||
#define PHY_LPDDR4_RON_61ohm (18)
|
||||
#define PHY_LPDDR4_RON_55ohm (19)
|
||||
#define PHY_LPDDR4_RON_51ohm (20)
|
||||
#define PHY_LPDDR4_RON_47ohm (21)
|
||||
#define PHY_LPDDR4_RON_43ohm (22)
|
||||
#define PHY_LPDDR4_RON_40ohm (23)
|
||||
#define PHY_LPDDR4_RON_38ohm (24)
|
||||
#define PHY_LPDDR4_RON_36ohm (25)
|
||||
#define PHY_LPDDR4_RON_34ohm (26)
|
||||
#define PHY_LPDDR4_RON_32ohm (27)
|
||||
#define PHY_LPDDR4_RON_30ohm (28)
|
||||
#define PHY_LPDDR4_RON_29ohm (29)
|
||||
#define PHY_LPDDR4_RON_28ohm (30)
|
||||
#define PHY_LPDDR4_RON_26ohm (31)
|
||||
|
||||
#define PHY_LPDDR4_RTT_DISABLE (0)
|
||||
#define PHY_LPDDR4_RTT_998ohm (1)
|
||||
#define PHY_LPDDR4_RTT_506ohm (2)
|
||||
#define PHY_LPDDR4_RTT_336ohm (3)
|
||||
#define PHY_LPDDR4_RTT_253ohm (4)
|
||||
#define PHY_LPDDR4_RTT_202ohm (5)
|
||||
#define PHY_LPDDR4_RTT_169ohm (6)
|
||||
#define PHY_LPDDR4_RTT_144ohm (7)
|
||||
#define PHY_LPDDR4_RTT_127ohm (16)
|
||||
#define PHY_LPDDR4_RTT_112ohm (17)
|
||||
#define PHY_LPDDR4_RTT_101ohm (18)
|
||||
#define PHY_LPDDR4_RTT_92ohm (19)
|
||||
#define PHY_LPDDR4_RTT_84ohm (20)
|
||||
#define PHY_LPDDR4_RTT_78ohm (21)
|
||||
#define PHY_LPDDR4_RTT_72ohm (22)
|
||||
#define PHY_LPDDR4_RTT_67ohm (23)
|
||||
#define PHY_LPDDR4_RTT_63ohm (24)
|
||||
#define PHY_LPDDR4_RTT_60ohm (25)
|
||||
#define PHY_LPDDR4_RTT_56ohm (26)
|
||||
#define PHY_LPDDR4_RTT_53ohm (27)
|
||||
#define PHY_LPDDR4_RTT_51ohm (28)
|
||||
#define PHY_LPDDR4_RTT_48ohm (29)
|
||||
#define PHY_LPDDR4_RTT_46ohm (30)
|
||||
#define PHY_LPDDR4_RTT_44ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RV1126_POWER_H__
|
||||
|
||||
/* VD_CORE */
|
||||
#define RV1126_PD_CPU_0 0
|
||||
#define RV1126_PD_CPU_1 1
|
||||
#define RV1126_PD_CPU_2 2
|
||||
#define RV1126_PD_CPU_3 3
|
||||
#define RV1126_PD_CORE_ALIVE 4
|
||||
|
||||
/* VD_PMU */
|
||||
#define RV1126_PD_PMU 5
|
||||
#define RV1126_PD_PMU_ALIVE 6
|
||||
|
||||
/* VD_NPU */
|
||||
#define RV1126_PD_NPU 7
|
||||
|
||||
/* VD_VEPU */
|
||||
#define RV1126_PD_VEPU 8
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RV1126_PD_VI 9
|
||||
#define RV1126_PD_VO 10
|
||||
#define RV1126_PD_ISPP 11
|
||||
#define RV1126_PD_VDPU 12
|
||||
#define RV1126_PD_CRYPTO 13
|
||||
#define RV1126_PD_DDR 14
|
||||
#define RV1126_PD_NVM 15
|
||||
#define RV1126_PD_SDIO 16
|
||||
#define RV1126_PD_USB 17
|
||||
#define RV1126_PD_LOGIC_ALIVE 18
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2017 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H
|
||||
#define _DT_BINDINGS_SOC_ROCKCHIP_SYSTEM_STATUS_H
|
||||
|
||||
#define SYS_STATUS_NORMAL (1 << 0)
|
||||
#define SYS_STATUS_SUSPEND (1 << 1)
|
||||
#define SYS_STATUS_IDLE (1 << 2)
|
||||
#define SYS_STATUS_REBOOT (1 << 3)
|
||||
#define SYS_STATUS_VIDEO_4K (1 << 4)
|
||||
#define SYS_STATUS_VIDEO_1080P (1 << 5)
|
||||
#define SYS_STATUS_GPU (1 << 6)
|
||||
#define SYS_STATUS_RGA (1 << 7)
|
||||
#define SYS_STATUS_CIF0 (1 << 8)
|
||||
#define SYS_STATUS_CIF1 (1 << 9)
|
||||
#define SYS_STATUS_LCDC0 (1 << 10)
|
||||
#define SYS_STATUS_LCDC1 (1 << 11)
|
||||
#define SYS_STATUS_BOOST (1 << 12)
|
||||
#define SYS_STATUS_PERFORMANCE (1 << 13)
|
||||
#define SYS_STATUS_ISP (1 << 14)
|
||||
#define SYS_STATUS_HDMI (1 << 15)
|
||||
#define SYS_STATUS_VIDEO_4K_10B (1 << 16)
|
||||
#define SYS_STATUS_LOW_POWER (1 << 17)
|
||||
|
||||
#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \
|
||||
SYS_STATUS_VIDEO_1080P | \
|
||||
SYS_STATUS_VIDEO_4K_10B)
|
||||
#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue