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clk: rockchip: rv1126: Add support to init hpll and 32k 

Change-Id: If41a708d925c978e8db1e21b23c16d9a9a2e29d8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2020-04-14 16:28:43 +08:00
parent b77d2f1647
commit 56a06ac82e
2 changed files with 20 additions and 0 deletions
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2
arch/arm/include/asm/arch-rockchip/cru_rv1126.h
View File

@ -25,6 +25,7 @@
#define HCLK_PDPHP_HZ (200 * MHz)
#define HCLK_PDCORE_HZ (200 * MHz)
#define HCLK_PDAUDIO_HZ (150 * MHz)
#define CLK_OSC0_DIV_HZ (32768)
/* RV1126 pll id */
enum rv1126_pll_id {
@ -53,6 +54,7 @@ struct rv1126_clk_priv {
struct rv1126_grf *grf;
ulong gpll_hz;
ulong cpll_hz;
ulong hpll_hz;
ulong armclk_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;

18
drivers/clk/rockchip/clk_rv1126.c
View File

@ -196,6 +196,9 @@ static ulong rv1126_rtc32k_set_pmuclk(struct rv1126_pmuclk_priv *priv,
struct rv1126_pmucru *pmucru = priv->pmucru;
unsigned long m, n, val;
rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK,
RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT);
rational_best_approximation(rate, OSC_HZ,
GENMASK(16 - 1, 0),
GENMASK(16 - 1, 0),
@ -1304,6 +1307,10 @@ static ulong rv1126_clk_get_rate(struct clk *clk)
rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru,
CPLL);
break;
case PLL_HPLL:
rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru,
HPLL);
break;
case HCLK_PDCORE_NIU:
rate = rv1126_pdcore_get_clk(priv);
break;
@ -1391,6 +1398,10 @@ static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate)
ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru,
CPLL, rate);
break;
case PLL_HPLL:
ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru,
HPLL, rate);
break;
case ACLK_PDBUS:
case HCLK_PDBUS:
case PCLK_PDBUS:
@ -1713,6 +1724,7 @@ static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate)
}
rv1126_pdpmu_set_pmuclk(pmu_priv, PCLK_PDPMU_HZ);
rv1126_rtc32k_set_pmuclk(pmu_priv, CLK_OSC0_DIV_HZ);
return 0;
}
@ -1740,6 +1752,12 @@ static void rv1126_clk_init(struct rv1126_clk_priv *priv)
if (!ret)
priv->cpll_hz = CPLL_HZ;
}
if (priv->hpll_hz != HPLL_HZ) {
ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru,
HPLL, HPLL_HZ);
if (!ret)
priv->hpll_hz = HPLL_HZ;
}
if (priv->gpll_hz != GPLL_HZ)
rv1126_gpll_set_clk(priv, GPLL_HZ);