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clk: rockchip: rk3288: add clk_set_default 

support aclk_vio\hclk_vio clk setting.

Change-Id: Ie826c770670598161f22208f504d8762b8597811
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-01-24 11:11:19 +08:00 committed by Kever Yang
parent 544e79360d
commit 5561190119
3 changed files with 46 additions and 26 deletions
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30
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
View File

@ -25,6 +25,8 @@
#define PERI_HCLK_HZ 148500000 #define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000 #define PERI_PCLK_HZ 74250000
#define HCLK_VIO_HZ 100000000
/* Private data for the clock driver - used by rockchip_get_cru() */ /* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3288_clk_priv { struct rk3288_clk_priv {
struct rk3288_grf *grf; struct rk3288_grf *grf;
@ -155,6 +157,12 @@ enum {
DCLK_VOP0_SELECT_NPLL = 2, DCLK_VOP0_SELECT_NPLL = 2,
}; };
/* CRU_CLKSEL28_CON */
enum {
HCLK_VIO_DIV_SHIFT = 8,
HCLK_VIO_DIV_MASK = 0x1f << HCLK_VIO_DIV_SHIFT,
};
/* CRU_CLKSEL29_CON */ /* CRU_CLKSEL29_CON */
enum { enum {
DCLK_VOP1_DIV_SHIFT = 8, DCLK_VOP1_DIV_SHIFT = 8,
@ -168,17 +176,17 @@ enum {
/* CRU_CLKSEL31_CON */ /* CRU_CLKSEL31_CON */
enum { enum {
ACLK_VOP_SELECT_CPLL = 0, ACLK_VIO_SELECT_CPLL = 0,
ACLK_VOP_SELECT_GPLL = 1, ACLK_VIO_SELECT_GPLL = 1,
ACLK_VOP_SELECT_USB480 = 2, ACLK_VIO_SELECT_USB480 = 2,
ACLK_VOP1_PLL_SHIFT = 14, ACLK_VIO1_PLL_SHIFT = 14,
ACLK_VOP1_PLL_MASK = 3 << ACLK_VOP1_PLL_SHIFT, ACLK_VIO1_PLL_MASK = 3 << ACLK_VIO1_PLL_SHIFT,
ACLK_VOP1_DIV_SHIFT = 8, ACLK_VIO1_DIV_SHIFT = 8,
ACLK_VOP1_DIV_MASK = 0x1f << ACLK_VOP1_DIV_SHIFT, ACLK_VIO1_DIV_MASK = 0x1f << ACLK_VIO1_DIV_SHIFT,
ACLK_VOP0_PLL_SHIFT = 6, ACLK_VIO0_PLL_SHIFT = 6,
ACLK_VOP0_PLL_MASK = 3 << ACLK_VOP0_PLL_SHIFT, ACLK_VIO0_PLL_MASK = 3 << ACLK_VIO0_PLL_SHIFT,
ACLK_VOP0_DIV_SHIFT = 0, ACLK_VIO0_DIV_SHIFT = 0,
ACLK_VOP0_DIV_MASK = 0x1f << ACLK_VOP0_DIV_SHIFT, ACLK_VIO0_DIV_MASK = 0x1f << ACLK_VIO0_DIV_SHIFT,
}; };
/* CRU_CLKSEL37_CON */ /* CRU_CLKSEL37_CON */

40
drivers/clk/rockchip/clk_rk3288.c
View File

@ -406,7 +406,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
struct pll_div cpll_config = {0}; struct pll_div cpll_config = {0};
u32 lcdc_div, parent; u32 lcdc_div, parent;
int ret; int ret;
unsigned int gpll_rate, npll_rate, cpll_rate; unsigned int gpll_rate, npll_rate;
gpll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); gpll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
npll_rate = rkclk_pll_get_rate(cru, CLK_NEW); npll_rate = rkclk_pll_get_rate(cru, CLK_NEW);
@ -488,21 +488,24 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
((lcdc_div - 1) << DCLK_VOP1_DIV_SHIFT) | ((lcdc_div - 1) << DCLK_VOP1_DIV_SHIFT) |
(parent << DCLK_VOP1_PLL_SHIFT)); (parent << DCLK_VOP1_PLL_SHIFT));
break; break;
case ACLK_VOP0: case ACLK_VIO0:
cpll_rate = rkclk_pll_get_rate(cru, CLK_CODEC); lcdc_div = DIV_ROUND_UP(gpll_rate, rate_hz);
lcdc_div = DIV_ROUND_UP(cpll_rate, rate_hz);
rk_clrsetreg(&cru->cru_clksel_con[31], rk_clrsetreg(&cru->cru_clksel_con[31],
ACLK_VOP0_PLL_MASK | ACLK_VOP0_DIV_MASK, ACLK_VIO0_PLL_MASK | ACLK_VIO0_DIV_MASK,
ACLK_VOP_SELECT_CPLL << ACLK_VOP0_PLL_SHIFT | ACLK_VIO_SELECT_GPLL << ACLK_VIO0_PLL_SHIFT |
(lcdc_div - 1) << ACLK_VOP0_DIV_SHIFT); (lcdc_div - 1) << ACLK_VIO0_DIV_SHIFT);
break; break;
case ACLK_VOP1: case ACLK_VIO1:
cpll_rate = rkclk_pll_get_rate(cru, CLK_CODEC); lcdc_div = DIV_ROUND_UP(gpll_rate, rate_hz);
lcdc_div = DIV_ROUND_UP(cpll_rate, rate_hz);
rk_clrsetreg(&cru->cru_clksel_con[31], rk_clrsetreg(&cru->cru_clksel_con[31],
ACLK_VOP1_PLL_MASK | ACLK_VOP1_DIV_MASK, ACLK_VIO1_PLL_MASK | ACLK_VIO1_DIV_MASK,
ACLK_VOP_SELECT_CPLL << ACLK_VOP1_PLL_SHIFT | ACLK_VIO_SELECT_GPLL << ACLK_VIO1_PLL_SHIFT |
(lcdc_div - 1) << ACLK_VOP1_DIV_SHIFT); (lcdc_div - 1) << ACLK_VIO1_DIV_SHIFT);
lcdc_div = DIV_ROUND_UP(rate_hz, HCLK_VIO_HZ);
rk_clrsetreg(&cru->cru_clksel_con[28],
HCLK_VIO_DIV_MASK,
(lcdc_div - 1) << HCLK_VIO_DIV_SHIFT);
break; break;
} }
@ -956,8 +959,8 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
break; break;
case DCLK_VOP0: case DCLK_VOP0:
case DCLK_VOP1: case DCLK_VOP1:
case ACLK_VOP0: case ACLK_VIO0:
case ACLK_VOP1: case ACLK_VIO1:
new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
break; break;
case SCLK_EDP_24M: case SCLK_EDP_24M:
@ -1244,6 +1247,7 @@ static int rk3288_clk_probe(struct udevice *dev)
{ {
struct rk3288_clk_priv *priv = dev_get_priv(dev); struct rk3288_clk_priv *priv = dev_get_priv(dev);
bool init_clocks = false; bool init_clocks = false;
int ret;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(priv->grf)) if (IS_ERR(priv->grf))
@ -1287,6 +1291,12 @@ static int rk3288_clk_probe(struct udevice *dev)
priv->armclk_init_hz = priv->armclk_enter_hz; priv->armclk_init_hz = priv->armclk_enter_hz;
} }
ret = clk_set_defaults(dev);
if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret);
else
priv->sync_kernel = true;
return 0; return 0;
} }

2
include/dt-bindings/clock/rk3288-cru.h
View File

@ -105,6 +105,8 @@
#define ACLK_VCODEC 208 #define ACLK_VCODEC 208
#define ACLK_CPU 209 #define ACLK_CPU 209
#define ACLK_PERI 210 #define ACLK_PERI 210
#define ACLK_VIO0 211
#define ACLK_VIO1 212
/* pclk gates */ /* pclk gates */
#define PCLK_GPIO0 320 #define PCLK_GPIO0 320