arm: armv7: introduce cpu suspend and resume support
Just like linux, it supports cpu save and restore context during enter and exit low power mode. With this patch, cpu is able to suspend with core power off. Workflow for trap into ATF for system suspend: cpu_suspend -> cpu_do_suspend -> arch specific fn: int (*fn)(unsigned long) -> psci_system_suspend(deliver 'cpu_resume()' address to ATF) -> ATF system suspend <- ATF system resume <- cpu_resume <- cpu_do_resume next instruction Notice: If needed, you should remember to save and restore GIC by yourself. Change-Id: I5cb6fb6ac5b6a7f4ec4a975b0fc38250b000b28e Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This commit is contained in:
Joseph Chen
Kever Yang
parent
6f00aaa207
commit
5492555290
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@ -12,6 +12,11 @@ obj-y += cache_v7.o cache_v7_asm.o
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obj-y += cpu.o cp15.o
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obj-y += syslib.o
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ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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obj-y += suspend.o
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obj-y += sleep.o
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endif
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ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
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obj-y += lowlevel_init.o
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endif
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@ -0,0 +1,185 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arm32_macros.S>
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#include <asm/macro.h>
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#include <asm-offsets.h>
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#include <asm/psci.h>
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#include <config.h>
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#include <linux/linkage.h>
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.globl cpu_suspend
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.globl cpu_do_suspend
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.globl cpu_suspend_save
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.globl cpu_resume
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.globl cpu_do_resume
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/*
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* int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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* @arg will be passed to fn as argument
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* return value: 0 - cpu resumed from suspended state.
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* -1 - cpu not suspended.
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*/
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ENTRY(cpu_suspend)
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push {r4 - r12, lr}
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mov r5, sp
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sub sp, sp, #PM_CTX_SIZE
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push {r0, r1}
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/* r9 is gd, save it to _suspend_gd !!! */
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adr r4, _suspend_gd
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str r9, [r4]
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mov r1, r5
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add r0, sp, #8
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blx cpu_suspend_save
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adr lr, aborted
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/* Jump to arch specific suspend */
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pop {r0, pc}
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aborted:
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/* cpu not suspended */
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add sp, sp, #PM_CTX_SIZE
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/* Return -1 to the caller */
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mov r0, #(-1)
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suspend_return:
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pop {r4 - r12, pc}
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ENDPROC(cpu_suspend)
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ENTRY(cpu_do_suspend)
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push {r4 - r11}
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read_midr r4
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ubfx r5, r4, #4, #12
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ldr r4, CORTEX_A7_PART_NUM
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cmp r5, r4
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beq a7_suspend
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ldr r4, CORTEX_A9_PART_NUM
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cmp r5, r4
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beq a9_suspend
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/* cpu not supported */
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b .
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/* A9 needs PCR/DIAG */
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a9_suspend:
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read_pcr r4
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read_diag r5
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stmia r0!, {r4 - r5}
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a7_suspend:
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read_fcseidr r4
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read_tpidruro r5
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stmia r0!, {r4 - r5}
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read_dacr r4
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read_ttbr0 r5
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read_ttbr1 r6
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read_ttbcr r7
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read_sctlr r8
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read_actlr r9
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read_cpacr r10
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stmia r0!, {r4 - r10}
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read_prrr r4
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read_nmrr r5
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read_vbar r6
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mrs r7, CPSR
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stmia r0, {r4 - r7}
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pop {r4 - r11}
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bx lr
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ENDPROC(cpu_do_suspend)
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ENTRY(cpu_resume)
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/* Disable interrupt */
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cpsid aif
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/* Load gd !! */
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adr r1, _suspend_gd
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ldr r2, [r1]
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/* Get pm_ctx */
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add r2, r2, #PM_CTX_PHYS
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ldr r0, [r2]
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/* Need to use r0!, because cpu_do_resume needs it */
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ldmia r0!, {sp, pc}
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ENDPROC(cpu_resume)
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/*
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* void sm_do_cpu_do_resume(paddr suspend_regs) __noreturn;
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* Restore the registers stored when cpu_do_suspend
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* r0 points to the physical base address of the suspend_regs
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* field of struct pm_ctx.
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*/
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ENTRY(cpu_do_resume)
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read_midr r4
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ubfx r5, r4, #4, #12
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ldr r4, CORTEX_A7_PART_NUM
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cmp r5, r4
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beq a7_resume
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/*
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* A9 needs PCR/DIAG
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*/
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ldmia r0!, {r4 - r5}
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write_pcr r4
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write_diag r5
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a7_resume:
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/* v7 resume */
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mov ip, #0
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/* Invalidate icache to PoU */
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write_iciallu
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/* set reserved context */
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write_contextidr ip
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ldmia r0!, {r4 - r5}
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write_fcseidr r4
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write_tpidruro r5
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ldmia r0!, {r4 - r10}
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/* Invalidate entire TLB */
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write_tlbiall
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write_dacr r4
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write_ttbr0 r5
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write_ttbr1 r6
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write_ttbcr r7
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ldmia r0, {r4 - r7}
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write_prrr r4
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write_nmrr r5
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write_vbar r6
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write_actlr r9
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write_cpacr r10
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write_bpiall
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isb
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dsb
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/* MMU will be enabled here */
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write_sctlr r8
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isb
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/* Restore interrupt */
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msr CPSR_c, r7
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mov r0, #0
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b suspend_return
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ENDPROC(cpu_do_resume)
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.align 4
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_suspend_gd:
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.word 0x0
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CORTEX_A7_PART_NUM:
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.word 0xC07
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CORTEX_A9_PART_NUM:
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.word 0xC09
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@ -0,0 +1,23 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/suspend.h>
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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void cpu_suspend_save(struct pm_ctx *ctx, unsigned long sp)
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{
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gd->pm_ctx_phys = (phys_addr_t)ctx;
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/* The content will be passed to cpu_do_resume as register sp */
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ctx->sp = sp;
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ctx->cpu_resume_addr = (phys_addr_t)cpu_do_resume;
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cpu_do_suspend(ctx->suspend_regs);
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flush_dcache_all();
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}
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@ -0,0 +1,264 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Please keep them sorted based on the CRn register */
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.macro read_midr reg
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mrc p15, 0, \reg, c0, c0, 0
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.endm
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.macro read_ctr reg
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mrc p15, 0, \reg, c0, c0, 1
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.endm
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.macro read_mpidr reg
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mrc p15, 0, \reg, c0, c0, 5
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.endm
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.macro read_sctlr reg
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mrc p15, 0, \reg, c1, c0, 0
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.endm
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.macro write_sctlr reg
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mcr p15, 0, \reg, c1, c0, 0
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.endm
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.macro write_actlr reg
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mcr p15, 0, \reg, c1, c0, 1
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.endm
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.macro read_actlr reg
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mrc p15, 0, \reg, c1, c0, 1
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.endm
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.macro write_cpacr reg
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mcr p15, 0, \reg, c1, c0, 2
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.endm
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.macro read_cpacr reg
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mrc p15, 0, \reg, c1, c0, 2
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.endm
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.macro read_scr reg
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mrc p15, 0, \reg, c1, c1, 0
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.endm
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.macro write_scr reg
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mcr p15, 0, \reg, c1, c1, 0
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.endm
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.macro write_nsacr reg
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mcr p15, 0, \reg, c1, c1, 2
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.endm
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.macro read_nsacr reg
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mrc p15, 0, \reg, c1, c1, 2
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.endm
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.macro write_ttbr0 reg
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mcr p15, 0, \reg, c2, c0, 0
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.endm
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.macro read_ttbr0 reg
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mrc p15, 0, \reg, c2, c0, 0
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.endm
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.macro write_ttbr1 reg
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mcr p15, 0, \reg, c2, c0, 1
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.endm
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.macro read_ttbr1 reg
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mrc p15, 0, \reg, c2, c0, 1
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.endm
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.macro write_ttbcr reg
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mcr p15, 0, \reg, c2, c0, 2
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.endm
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.macro read_ttbcr reg
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mrc p15, 0, \reg, c2, c0, 2
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.endm
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.macro write_dacr reg
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mcr p15, 0, \reg, c3, c0, 0
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.endm
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.macro read_dacr reg
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mrc p15, 0, \reg, c3, c0, 0
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.endm
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.macro read_dfsr reg
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mrc p15, 0, \reg, c5, c0, 0
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.endm
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.macro write_icialluis
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/*
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* Invalidate all instruction caches to PoU, Inner Shareable
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* (register ignored)
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*/
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mcr p15, 0, r0, c7, c1, 0
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.endm
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.macro write_bpiallis
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/*
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* Invalidate entire branch predictor array, Inner Shareable
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* (register ignored)
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*/
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mcr p15, 0, r0, c7, c1, 6
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.endm
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.macro write_iciallu
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/* Invalidate all instruction caches to PoU (register ignored) */
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mcr p15, 0, r0, c7, c5, 0
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.endm
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.macro write_icimvau reg
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/* Instruction cache invalidate by MVA */
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mcr p15, 0, \reg, c7, c5, 1
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.endm
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.macro write_bpiall
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/* Invalidate entire branch predictor array (register ignored) */
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mcr p15, 0, r0, c7, c5, 6
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.endm
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.macro write_dcimvac reg
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/* Data cache invalidate by MVA */
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mcr p15, 0, \reg, c7, c6, 1
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.endm
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.macro write_dcisw reg
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/* Data cache invalidate by set/way */
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mcr p15, 0, \reg, c7, c6, 2
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.endm
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.macro write_dccmvac reg
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/* Data cache clean by MVA */
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mcr p15, 0, \reg, c7, c10, 1
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.endm
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.macro write_dccsw reg
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/* Data cache clean by set/way */
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mcr p15, 0, \reg, c7, c10, 2
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.endm
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.macro write_dccimvac reg
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/* Data cache invalidate by MVA */
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mcr p15, 0, \reg, c7, c14, 1
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.endm
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.macro write_dccisw reg
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/* Data cache clean and invalidate by set/way */
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mcr p15, 0, \reg, c7, c14, 2
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.endm
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.macro write_tlbiall
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/* Invalidate entire unified TLB (register ignored) */
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mcr p15, 0, r0, c8, c7, 0
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.endm
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.macro write_tlbiallis
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/* Invalidate entire unified TLB Inner Sharable (register ignored) */
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mcr p15, 0, r0, c8, c3, 0
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.endm
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.macro write_tlbiasidis reg
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/* Invalidate unified TLB by ASID Inner Sharable */
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mcr p15, 0, \reg, c8, c3, 2
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.endm
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.macro write_tlbimvaais reg
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/* Invalidate unified TLB by MVA all ASID Inner Sharable */
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mcr p15, 0, \reg, c8, c3, 3
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.endm
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.macro write_prrr reg
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mcr p15, 0, \reg, c10, c2, 0
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.endm
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.macro read_prrr reg
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mrc p15, 0, \reg, c10, c2, 0
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.endm
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.macro write_nmrr reg
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mcr p15, 0, \reg, c10, c2, 1
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.endm
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.macro read_nmrr reg
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mrc p15, 0, \reg, c10, c2, 1
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.endm
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.macro read_vbar reg
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mrc p15, 0, \reg, c12, c0, 0
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.endm
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.macro write_vbar reg
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mcr p15, 0, \reg, c12, c0, 0
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.endm
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.macro write_mvbar reg
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mcr p15, 0, \reg, c12, c0, 1
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.endm
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.macro read_mvbar reg
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mrc p15, 0, \reg, c12, c0, 1
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.endm
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.macro write_fcseidr reg
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mcr p15, 0, \reg, c13, c0, 0
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.endm
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.macro read_fcseidr reg
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mrc p15, 0, \reg, c13, c0, 0
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.endm
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.macro write_contextidr reg
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mcr p15, 0, \reg, c13, c0, 1
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.endm
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.macro read_contextidr reg
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mrc p15, 0, \reg, c13, c0, 1
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.endm
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.macro write_tpidruro reg
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mcr p15, 0, \reg, c13, c0, 3
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.endm
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.macro read_tpidruro reg
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mrc p15, 0, \reg, c13, c0, 3
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.endm
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.macro read_clidr reg
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/* Cache Level ID Register */
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mrc p15, 1, \reg, c0, c0, 1
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.endm
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.macro read_ccsidr reg
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/* Cache Size ID Registers */
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mrc p15, 1, \reg, c0, c0, 0
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.endm
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.macro write_csselr reg
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/* Cache Size Selection Register */
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mcr p15, 2, \reg, c0, c0, 0
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.endm
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/* Cortex A9: pcr, diag registers */
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.macro write_pcr reg
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mcr p15, 0, \reg, c15, c0, 0
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.endm
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.macro read_pcr reg
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mrc p15, 0, \reg, c15, c0, 0
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.endm
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.macro write_diag reg
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mcr p15, 0, \reg, c15, c0, 1
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.endm
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.macro read_diag reg
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mrc p15, 0, \reg, c15, c0, 1
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.endm
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@ -0,0 +1,25 @@
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef SUSPEND_H
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#define SUSPEND_H
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#include <common.h>
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#include <asm-generic/global_data.h>
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/* suspend/resume core functions */
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void cpu_suspend_save(struct pm_ctx *ptr, unsigned long sp);
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void cpu_do_suspend(unsigned long *ptr);
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void cpu_resume(void);
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void cpu_do_resume(void);
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/*
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* Exported to platform suspend, arg will be passed to fn as r0
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* Return value: 0 - cpu resumed from suspended state.
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* -1 - cpu not suspended.
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*/
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int cpu_suspend(unsigned long arg, int (*fn)(unsigned long));
|
||||
#endif
|
||||
|
|
@ -24,6 +24,13 @@
|
|||
#include <membuff.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
/* Never change the sequence of members !!! */
|
||||
struct pm_ctx {
|
||||
unsigned long sp;
|
||||
phys_addr_t cpu_resume_addr;
|
||||
unsigned long suspend_regs[15];
|
||||
};
|
||||
|
||||
typedef struct global_data {
|
||||
bd_t *bd;
|
||||
unsigned long flags;
|
||||
|
|
@ -114,6 +121,7 @@ typedef struct global_data {
|
|||
struct bootstage_data *bootstage; /* Bootstage information */
|
||||
struct bootstage_data *new_bootstage; /* Relocated bootstage info */
|
||||
#endif
|
||||
phys_addr_t pm_ctx_phys;
|
||||
} gd_t;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -38,5 +38,8 @@ int main(void)
|
|||
|
||||
DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp));
|
||||
|
||||
DEFINE(PM_CTX_SIZE, sizeof(struct pm_ctx));
|
||||
DEFINE(PM_CTX_PHYS, offsetof(struct global_data, pm_ctx_phys));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue