rockchip: Add RV1108 SPL support
add rv1108 spl support so we can load u-boot from SPL Change-Id: I9d36cd590a22d26a46dd84bc3ee0c761048f7b01 Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He
Kever Yang
parent
95b95808a8
commit
52f7b21d4b
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@ -214,6 +214,8 @@ config ROCKCHIP_RK3399
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config ROCKCHIP_RV1108
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bool "Support Rockchip RV1108"
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select CPU_V7
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select SUPPORT_SPL
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select SPL
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help
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The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
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and a DSP.
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@ -12,8 +12,12 @@
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int rockchip_get_clk(struct udevice **devp)
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{
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#ifndef CONFIG_SPL_BUILD
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return uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(clk_rv1108), devp);
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#else
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return -1;
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#endif
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}
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void *rockchip_get_cru(void)
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@ -1,7 +1,34 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd
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* Author: Zhihuan He <huan.he@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rv1108.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0x10300000
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void board_debug_uart_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct rv1108_grf *grf = (void *)GRF_BASE;
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0x10230000)
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rk_clrsetreg(&grf->gpio3a_iomux, /* UART0 */
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GPIO3A6_MASK | GPIO3A5_MASK,
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GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
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GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
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#else
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rk_clrsetreg(&grf->gpio2d_iomux, /* UART2 */
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GPIO2D2_MASK | GPIO2D1_MASK,
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GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
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GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
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#endif
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#endif /*CONFIG_SPL_BUILD*/
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}
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@ -40,6 +40,7 @@ struct tos_parameter_t {
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s64 reserve[8];
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};
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#if defined(CONFIG_SPL_FRAMEWORK) || !defined(CONFIG_SPL_OF_PLATDATA)
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int dram_init_banksize(void)
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{
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size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
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@ -66,6 +67,7 @@ int dram_init_banksize(void)
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return 0;
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}
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#endif
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size_t rockchip_sdram_size(phys_addr_t reg)
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{
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@ -107,6 +109,7 @@ size_t rockchip_sdram_size(phys_addr_t reg)
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return (size_t)size_mb << 20;
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}
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#if defined(CONFIG_SPL_FRAMEWORK) || !defined(CONFIG_SPL_OF_PLATDATA)
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int dram_init(void)
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{
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struct ram_info ram;
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@ -129,6 +132,7 @@ int dram_init(void)
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return 0;
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}
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#endif
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ulong board_get_usable_ram_top(ulong total_size)
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{
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@ -10,6 +10,7 @@
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#include <ram.h>
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#include <spl.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch-rockchip/sys_proto.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -1,10 +1,18 @@
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CONFIG_ARM=y
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# CONFIG_SPL_USE_ARCH_MEMCPY is not set
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# CONFIG_SPL_USE_ARCH_MEMSET is not set
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ROCKCHIP_RV1108=y
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CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_TARGET_EVB_RV1108=y
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
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CONFIG_DEBUG_UART=y
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_FASTBOOT=y
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CONFIG_USB_FUNCTION_FASTBOOT=y
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CONFIG_CMD_FASTBOOT=y
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@ -19,6 +27,8 @@ CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_SPL_OF_PLATDATA=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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@ -37,12 +47,15 @@ CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PINCTRL=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_DM_RESET=y
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CONFIG_BAUDRATE=1500000
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# CONFIG_SPL_SERIAL_PRESENT is not set
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CONFIG_DEBUG_UART_BASE=0x10210000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_ROCKCHIP_SFC=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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@ -58,4 +71,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_G_DNL_MANUFACTURER="Rockchip"
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CONFIG_G_DNL_VENDOR_NUM=0x2207
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CONFIG_G_DNL_PRODUCT_NUM=0x110a
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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@ -14,11 +14,20 @@
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
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/* SPL support */
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#define CONFIG_SPL_STACK 0x10080700
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#define CONFIG_SPL_TEXT_BASE 0x10080800
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#define CONFIG_SPL_MAX_SIZE 0x1700
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/* BSS setup */
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#define CONFIG_SPL_BSS_MAX_SIZE 0x100
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#define CONFIG_ROCKUSB_G_DNL_PID 0x110A
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#define CONFIG_BOUNCE_BUFFER
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