drm/rockchip: vop2: add support port1 to mipi dsi
Signed-off-by: Sandy Huang <hjc@rock-chips.com> Change-Id: Iee86d5da9df9ae185b261a46e3919375f8f0fd2d
This commit is contained in:
Sandy Huang
Huang Jiachai
parent
926664c9a0
commit
52ee18acb8
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@ -460,6 +460,11 @@
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#define RK3568_MAX_REG 0x1ED0
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#define RK3568_GRF_VO_CON1 0x0364
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#define GRF_BT656_CLK_INV_SHIFT 1
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#define GRF_BT1120_CLK_INV_SHIFT 2
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#define GRF_RGB_DCLK_INV_SHIFT 3
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#define VOP2_LAYER_MAX 8
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#define VOP2_MAX_VP 4
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@ -492,17 +497,6 @@ enum dither_down_mode {
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RGB888_TO_RGB666 = 0x1
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};
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struct vop2_reg {
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uint32_t mask;
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uint32_t offset:12;
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uint32_t shift:5;
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uint32_t write_mask:1;
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};
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struct vop2_grf_ctrl {
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struct vop2_reg dclk_inv;
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};
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enum vop2_video_ports_id {
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VOP2_VP0,
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VOP2_VP1,
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@ -528,7 +522,7 @@ struct vop2_win {
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};
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struct vop2_data {
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uint32_t version;
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u32 version;
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struct vop_rect max_output[VOP2_MAX_VP];
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/**
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* win_id: id of window attach to VP0,VP1,VP2,VP3,
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@ -543,15 +537,14 @@ struct vop2_data {
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*
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*/
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uint8_t win_sel_id[VOP2_LAYER_MAX];
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struct vop2_grf_ctrl *grf_ctrl;
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};
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struct vop2 {
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u32 *regsbak;
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void *regs;
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void *grf;
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uint32_t reg_len;
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uint32_t version;
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u32 reg_len;
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u32 version;
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const struct vop2_data *data;
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/**
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* @nr_wins: active wins attached to the video port
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@ -574,19 +567,19 @@ static inline uint16_t scl_cal_scale2(int src, int dst)
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return ((src - 1) << 12) / (dst - 1);
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}
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static inline void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v)
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static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
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{
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writel(v, vop2->regs + offset);
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vop2->regsbak[offset >> 2] = v;
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}
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static inline uint32_t vop2_readl(struct vop2 *vop2, uint32_t offset)
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static inline u32 vop2_readl(struct vop2 *vop2, u32 offset)
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{
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return readl(vop2->regs + offset);
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}
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static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
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uint32_t mask, uint32_t shift, uint32_t v,
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static inline void vop2_mask_write(struct vop2 *vop2, u32 offset,
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u32 mask, u32 shift, u32 v,
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bool write_mask)
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{
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if (!mask)
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@ -595,7 +588,7 @@ static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
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if (write_mask) {
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v = ((v & mask) << shift) | (mask << (shift + 16));
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} else {
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uint32_t cached_val = vop2->regsbak[offset >> 2];
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u32 cached_val = vop2->regsbak[offset >> 2];
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v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
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vop2->regsbak[offset >> 2] = v;
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@ -604,12 +597,21 @@ static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
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writel(v, vop2->regs + offset);
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}
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static inline void vop2_grf_writel(struct vop2 *vop, u32 offset,
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u32 mask, u32 shift, u32 v)
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{
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u32 val = 0;
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val = (v << shift) | (mask << (shift + 16));
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writel(val, vop->grf + offset);
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}
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static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
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{
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return us * mode->clock / mode->htotal / 1000;
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}
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static bool is_yuv_output(uint32_t bus_format)
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static bool is_yuv_output(u32 bus_format)
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{
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switch (bus_format) {
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case MEDIA_BUS_FMT_YUV8_1X24:
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@ -642,7 +644,7 @@ static int vop2_convert_csc_mode(int csc_mode)
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}
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}
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static __maybe_unused bool is_uv_swap(uint32_t bus_format, uint32_t output_mode)
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static __maybe_unused bool is_uv_swap(u32 bus_format, u32 output_mode)
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{
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/*
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* FIXME:
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@ -672,6 +674,8 @@ static void vop2_post_config(struct display_state *state, struct vop2 *vop2)
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{
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struct connector_state *conn_state = &state->conn_state;
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struct drm_display_mode *mode = &conn_state->mode;
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struct crtc_state *cstate = &state->crtc_state;
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u32 vp_offset = (cstate->crtc_id * 0x100);
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u16 vtotal = mode->crtc_vtotal;
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u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
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u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
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@ -697,18 +701,18 @@ static void vop2_post_config(struct display_state *state, struct vop2 *vop2)
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val = hact_st << 16;
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val |= hact_end;
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vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO, val);
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vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val);
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vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200;
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vact_end = vact_st + vsize;
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val = vact_st << 16;
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val |= vact_end;
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vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO, val);
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vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val);
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val = scl_cal_scale2(vdisplay, vsize) << 16;
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val |= scl_cal_scale2(hdisplay, hsize);
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vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB, val);
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vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val);
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#define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0)
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#define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1)
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vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL,
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vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset,
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POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) |
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POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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@ -716,21 +720,21 @@ static void vop2_post_config(struct display_state *state, struct vop2 *vop2)
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u16 vact_end_f1 = vact_st_f1 + vsize;
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val = vact_st_f1 << 16 | vact_end_f1;
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vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1, val);
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vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);
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}
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bg_ovl_dly = (nr_mixers - used_layer) << 1;
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bg_dly = pre_scan_max_dly - bg_ovl_dly;
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pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
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pre_scan_dly = (pre_scan_dly << 16) | hsync_len;
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vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING, pre_scan_dly);
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vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + vp_offset, pre_scan_dly);
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}
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static void vop2_layer_map_initial(struct vop2 *vop2)
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{
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struct vop2_layer *layer;
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struct vop2_win *win;
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uint32_t layer_map, sel;
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u32 layer_map, sel;
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int i, j;
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layer_map = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
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@ -850,7 +854,7 @@ static int rockchip_vop2_init(struct display_state *state)
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u16 vact_end = vact_st + vdisplay;
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bool yuv_overlay = false;
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//bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false;
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uint32_t vp_offset = (cstate->crtc_id * 0x100);
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u32 vp_offset = (cstate->crtc_id * 0x100);
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//struct clk dclk;
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//fdt_size_t len;
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u32 val;
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@ -861,7 +865,6 @@ static int rockchip_vop2_init(struct display_state *state)
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//uint8_t dither_down_mode = RGB888_TO_RGB666;
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vop2_initial(vop2, state);
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dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
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val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
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val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
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@ -874,14 +877,19 @@ static int rockchip_vop2_init(struct display_state *state)
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vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
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IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, !!dclk_inv,
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false);
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//VOP2_GRF_SET(vop2, dclk_inv, dclk_inv);
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vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK,
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GRF_RGB_DCLK_INV_SHIFT, !dclk_inv);
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}
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if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) {
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vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,
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1, false);
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vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK,
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BT1120_EN_SHIFT, 1, false);
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vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
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RGB_MUX_SHIFT, cstate->crtc_id, false);
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vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK,
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GRF_BT1120_CLK_INV_SHIFT, !dclk_inv);
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}
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if (conn_state->output_if & VOP_OUTPUT_IF_BT656) {
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@ -889,6 +897,8 @@ static int rockchip_vop2_init(struct display_state *state)
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1, false);
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vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
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RGB_MUX_SHIFT, cstate->crtc_id, false);
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vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK,
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GRF_BT656_CLK_INV_SHIFT, !dclk_inv);
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}
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if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) {
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@ -921,7 +931,6 @@ static int rockchip_vop2_init(struct display_state *state)
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}
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if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) {
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//cstate->crtc_id = 0;
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vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,
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1, false);
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vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
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@ -1132,9 +1141,15 @@ static void vop2_setup_win_for_vp(struct display_state *state)
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vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, shift,
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used_layers, false);
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if (port_id == 0) {
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vop2_writel(vop2, 0x604, 0x54760312);
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vop2_writel(vop2, 0x608, 0x84000781);
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vop2_writel(vop2, 0x6e0, 0x22000000);
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} else {
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vop2_writel(vop2, 0x604, 0x54720316);
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vop2_writel(vop2, 0x608, 0x84000708);
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vop2_writel(vop2, 0x6e4, 0x1e000000);
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}
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}
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static int rockchip_vop2_set_plane(struct display_state *state)
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@ -1153,8 +1168,8 @@ static int rockchip_vop2_set_plane(struct display_state *state)
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int xvir = cstate->xvir;
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int y_mirror = 0;
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int csc_mode;
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uint32_t win_offset = cstate->crtc_id * 0x200;
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uint32_t cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id);
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u32 win_offset = cstate->crtc_id * 0x200;
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u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id);
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if (crtc_w > cstate->max_output.width) {
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printf("ERROR: output w[%d] exceeded max width[%d]\n",
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@ -1218,8 +1233,8 @@ static int rockchip_vop2_enable(struct display_state *state)
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{
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struct crtc_state *cstate = &state->crtc_state;
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struct vop2 *vop2 = cstate->private;
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uint32_t vp_offset = (cstate->crtc_id * 0x100);
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uint32_t cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id);
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u32 vp_offset = (cstate->crtc_id * 0x100);
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u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id);
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vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
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STANDBY_EN_SHIFT, 0, false);
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@ -1232,8 +1247,8 @@ static int rockchip_vop2_disable(struct display_state *state)
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{
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struct crtc_state *cstate = &state->crtc_state;
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struct vop2 *vop2 = cstate->private;
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uint32_t vp_offset = (cstate->crtc_id * 0x100);
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uint32_t cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id);
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u32 vp_offset = (cstate->crtc_id * 0x100);
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u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id);
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vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
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STANDBY_EN_SHIFT, 1, false);
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