From 52db8715b401e3651c3b7e339b67de7dc5aff2fb Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Mon, 11 Nov 2019 17:08:08 +0800 Subject: [PATCH] video/drm: analogix_dp: Workaround async issue between pclk clock and 24m clock Background: - EDP software register bank is on the EDP 24m clock domain; - CPU access EDP software register bank, need to go through EDP APB read/write bus and EDP internal read/write bus; - EDP APB read/write bus is on the EDP pclk clock domain; - EDP internal read/write bus is on the EDP 24m clock domain; - Asynchronous logic circuit is added between APB read/write bus and Internal read/write bus; Issue: There is a bug on the Asynchronous logic circuit between APB read/write bus and Internal read/write bus; This bug will be random to cause the following wrong control/address signals sequence happen; - For write, maybe wrong register address is wrote in; - For read, maybe wrong register address is read out; Workaround: - For CPU write EDP register operation, write any register need following three steps, 1): Read EDP_BASE+0x00 dummy register firstly, latch the dummy register address on Reg_Address bus, to avoid next step write to wrong register to cause function register overrun; 2): 1st time to write the EDP register you want to operate, to latch the real write address on Reg_Address bus; 3): 2nd time to write the EDP register you want to operate, to make sure the data is write on the real write address; - For CPU read EDP register operation, read any register need following two steps, 1): 1st time to read the EDP register you want to operate, to latch the real read address on Reg_Address bus; 2): 2nd time to read the EDP register you want to operate, to make sure the data is read out from the real read address; Change-Id: I42613145b1d414321ac1aef290a35969a1461e36 Signed-off-by: Wyon Bi --- drivers/video/drm/analogix_dp_reg.c | 503 ++++++++++++++-------------- 1 file changed, 258 insertions(+), 245 deletions(-) diff --git a/drivers/video/drm/analogix_dp_reg.c b/drivers/video/drm/analogix_dp_reg.c index a38900b5b8..6204d0f1f3 100644 --- a/drivers/video/drm/analogix_dp_reg.c +++ b/drivers/video/drm/analogix_dp_reg.c @@ -33,18 +33,32 @@ #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) #define INT_STA_MASK INT_HPD +static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) +{ + readl(dp->reg_base); + writel(val, dp->reg_base + reg); + writel(val, dp->reg_base + reg); +} + +static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) +{ + readl(dp->reg_base + reg); + + return readl(dp->reg_base + reg); +} + void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) { u32 reg; if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); reg |= HDCP_VIDEO_MUTE; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); reg &= ~HDCP_VIDEO_MUTE; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); } } @@ -52,9 +66,9 @@ void analogix_dp_stop_video(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); reg &= ~VIDEO_EN; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); } void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) @@ -68,7 +82,7 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; - writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); + analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); } void analogix_dp_init_analog_param(struct analogix_dp_device *dp) @@ -76,10 +90,10 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) u32 reg; reg = TX_TERMINAL_CTRL_50_OHM; - writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); reg = SEL_24M | TX_DVDD_BIT_1_0625V; - writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); + analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); if (dp->plat_data.dev_type == ROCKCHIP_DP) { reg = REF_CLK_24M; @@ -87,43 +101,43 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) dp->plat_data.subdev_type == RK3368_EDP) reg ^= REF_CLK_MASK; - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); - writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); - writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); - writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); - writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); + analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); + analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x95); + analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); + analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); + analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); } reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; - writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); + analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | TX_CUR1_2X | TX_CUR_16_MA; - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); reg = CH3_AMP_400_MV | CH2_AMP_400_MV | CH1_AMP_400_MV | CH0_AMP_400_MV; - writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); } void analogix_dp_init_interrupt(struct analogix_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); + analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); /* Clear pending regisers */ - writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); - writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); - writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); - writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); - writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); /* 0:mask,1: unmask */ - writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); - writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); - writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); - writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); - writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); } void analogix_dp_reset(struct analogix_dp_device *dp) @@ -136,44 +150,44 @@ void analogix_dp_reset(struct analogix_dp_device *dp) reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N | SW_FUNC_EN_N; - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N; - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); udelay(30); analogix_dp_lane_swap(dp, 0); - writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); - writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); - writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); - writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); - writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); - writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); + analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); + analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); - writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); - writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); + analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); + analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); - writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); - writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); + analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); - writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); - writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); + analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); - writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); - writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); + analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); + analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); - writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); } void analogix_dp_swreset(struct analogix_dp_device *dp) { - writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); + analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); } void analogix_dp_config_interrupt(struct analogix_dp_device *dp) @@ -182,19 +196,19 @@ void analogix_dp_config_interrupt(struct analogix_dp_device *dp) /* 0: mask, 1: unmask */ reg = COMMON_INT_MASK_1; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); reg = COMMON_INT_MASK_2; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); reg = COMMON_INT_MASK_3; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); reg = COMMON_INT_MASK_4; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); reg = INT_STA_MASK; - writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); } void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) @@ -202,13 +216,13 @@ void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) u32 reg; /* 0: mask, 1: unmask */ - reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); reg &= ~COMMON_INT_MASK_4; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); + reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); reg &= ~INT_STA_MASK; - writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); } void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) @@ -217,17 +231,17 @@ void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) /* 0: mask, 1: unmask */ reg = COMMON_INT_MASK_4; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); reg = INT_STA_MASK; - writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); } enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -239,13 +253,13 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) u32 reg; if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); reg |= DP_PLL_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); + analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); reg &= ~DP_PLL_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); + analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); } } @@ -262,77 +276,77 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, switch (block) { case AUX_BLOCK: if (enable) { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg |= AUX_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg &= ~AUX_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } break; case CH0_BLOCK: if (enable) { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg |= CH0_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg &= ~CH0_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } break; case CH1_BLOCK: if (enable) { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg |= CH1_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg &= ~CH1_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } break; case CH2_BLOCK: if (enable) { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg |= CH2_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg &= ~CH2_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } break; case CH3_BLOCK: if (enable) { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg |= CH3_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg &= ~CH3_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } break; case ANALOG_TOTAL: if (enable) { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg |= DP_PHY_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - reg = readl(dp->reg_base + phy_pd_addr); + reg = analogix_dp_read(dp, phy_pd_addr); reg &= ~DP_PHY_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } break; case POWER_ALL: if (enable) { reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | CH1_PD | CH0_PD; - writel(reg, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, reg); } else { - writel(0x00, dp->reg_base + phy_pd_addr); + analogix_dp_write(dp, phy_pd_addr, 0x00); } break; default: @@ -348,11 +362,11 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp) analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); reg = PLL_LOCK_CHG; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); - writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); + analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); /* Power up PLL */ if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { @@ -370,10 +384,10 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N); - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); } void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) @@ -384,10 +398,10 @@ void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) return; reg = HOTPLUG_CHG | HPD_LOST | PLUG; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); reg = INT_HPD; - writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); } void analogix_dp_init_hpd(struct analogix_dp_device *dp) @@ -399,18 +413,18 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp) analogix_dp_clear_hotplug_interrupts(dp); - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); reg &= ~(F_HPD | HPD_CTRL); - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); } void analogix_dp_force_hpd(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); - reg = (F_HPD | HPD_CTRL); - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); + reg |= (F_HPD | HPD_CTRL); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); } enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) @@ -425,7 +439,7 @@ enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) return DP_IRQ_TYPE_HP_CABLE_OUT; } else { /* Parse hotplug interrupt status register */ - reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); + reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); if (reg & PLUG) return DP_IRQ_TYPE_HP_CABLE_IN; @@ -445,9 +459,9 @@ void analogix_dp_reset_aux(struct analogix_dp_device *dp) u32 reg; /* Disable AUX channel module */ - reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); reg |= AUX_FUNC_EN_N; - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); } void analogix_dp_init_aux(struct analogix_dp_device *dp) @@ -456,7 +470,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) /* Clear inerrupts related to AUX channel */ reg = RPLY_RECEIV | AUX_ERR; - writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); analogix_dp_reset_aux(dp); @@ -469,16 +483,16 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) | AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); + analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ reg = DEFER_CTRL_EN | DEFER_COUNT(1); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); /* Enable AUX channel module */ - reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); reg &= ~AUX_FUNC_EN_N; - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); } int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) @@ -489,7 +503,7 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) if (dm_gpio_get_value(&dp->hpd_gpio)) return 0; } else { - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); if (reg & HPD_STATUS) return 0; } @@ -501,9 +515,9 @@ void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); reg &= ~SW_FUNC_EN_N; - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); } int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) @@ -513,12 +527,12 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) int timeout_loop = 0; /* Enable AUX CH operation */ - reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); reg |= AUX_EN; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); /* Is AUX CH command reply received? */ - reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); + reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); while (!(reg & RPLY_RECEIV)) { timeout_loop++; if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { @@ -526,22 +540,22 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) return -ETIMEDOUT; } - reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); + reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); udelay(11); } /* Clear interrupt source for AUX CH command reply */ - writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); /* Clear interrupt source for AUX CH access error */ - reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); + reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); if (reg & AUX_ERR) { - writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); + analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); return -EREMOTEIO; } /* Check AUX CH error access status */ - reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); + reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); if ((reg & AUX_STATUS_MASK) != 0) { dev_err(dp->dev, "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); @@ -562,19 +576,19 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, for (i = 0; i < 3; i++) { /* Clear AUX CH data buffer */ reg = BUF_CLR; - writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); /* Select DPCD device address */ reg = AUX_ADDR_7_0(reg_addr); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); reg = AUX_ADDR_15_8(reg_addr); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); reg = AUX_ADDR_19_16(reg_addr); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); /* Write data buffer */ reg = (unsigned int)data; - writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg); /* * Set DisplayPort transaction and write 1 byte @@ -582,7 +596,7 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, * If Bit 3 is 0, I2C transaction. */ reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -604,15 +618,15 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, for (i = 0; i < 3; i++) { /* Clear AUX CH data buffer */ reg = BUF_CLR; - writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); /* Select DPCD device address */ reg = AUX_ADDR_7_0(reg_addr); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); reg = AUX_ADDR_15_8(reg_addr); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); reg = AUX_ADDR_19_16(reg_addr); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); /* * Set DisplayPort transaction and read 1 byte @@ -620,7 +634,7 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, * If Bit 3 is 0, I2C transaction. */ reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -629,7 +643,7 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, } /* Read data buffer */ - reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); *data = (unsigned char)(reg & 0xff); return retval; @@ -649,7 +663,7 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, /* Clear AUX CH data buffer */ reg = BUF_CLR; - writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); start_offset = 0; while (start_offset < count) { @@ -662,18 +676,17 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, for (i = 0; i < 3; i++) { /* Select DPCD device address */ reg = AUX_ADDR_7_0(reg_addr + start_offset); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); reg = AUX_ADDR_15_8(reg_addr + start_offset); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); reg = AUX_ADDR_19_16(reg_addr + start_offset); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); for (cur_data_idx = 0; cur_data_idx < cur_data_count; cur_data_idx++) { reg = data[start_offset + cur_data_idx]; - writel(reg, dp->reg_base + - ANALOGIX_DP_BUF_DATA_0 + - 4 * cur_data_idx); + analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + + 4 * cur_data_idx, reg); } /* @@ -683,7 +696,7 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, */ reg = AUX_LENGTH(cur_data_count) | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -711,7 +724,7 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, /* Clear AUX CH data buffer */ reg = BUF_CLR; - writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); start_offset = 0; while (start_offset < count) { @@ -725,11 +738,11 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, for (i = 0; i < 3; i++) { /* Select DPCD device address */ reg = AUX_ADDR_7_0(reg_addr + start_offset); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); reg = AUX_ADDR_15_8(reg_addr + start_offset); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); reg = AUX_ADDR_19_16(reg_addr + start_offset); - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); /* * Set DisplayPort transaction and read @@ -738,7 +751,7 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, */ reg = AUX_LENGTH(cur_data_count) | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -748,7 +761,7 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, for (cur_data_idx = 0; cur_data_idx < cur_data_count; cur_data_idx++) { - reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 + 4 * cur_data_idx); data[start_offset + cur_data_idx] = (unsigned char)reg; @@ -769,12 +782,12 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, /* Set EDID device address */ reg = device_addr; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); - writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); - writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); + analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); /* Set offset from base address of EDID device */ - writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); /* * Set I2C transaction and write address @@ -783,7 +796,7 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, */ reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | AUX_TX_COMM_WRITE; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -805,7 +818,7 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, for (i = 0; i < 3; i++) { /* Clear AUX CH data buffer */ reg = BUF_CLR; - writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); /* Select EDID device */ retval = analogix_dp_select_i2c_device(dp, device_addr, @@ -820,7 +833,7 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, */ reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_READ; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -830,7 +843,7 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, /* Read data */ if (retval == 0) - *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); + *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); return retval; } @@ -851,12 +864,12 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, for (j = 0; j < 3; j++) { /* Clear AUX CH data buffer */ reg = BUF_CLR; - writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); + analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); /* Set normal AUX CH command */ - reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); reg &= ~ADDR_ONLY; - writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); /* * If Rx sends defer, Tx sends only reads @@ -877,8 +890,8 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, reg = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_READ; - writel(reg, dp->reg_base + - ANALOGIX_DP_AUX_CH_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, + reg); /* Start AUX transaction */ retval = analogix_dp_start_aux_transaction(dp); @@ -886,7 +899,7 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, break; } /* Check if Rx sends defer */ - reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); + reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); if (reg == AUX_RX_COMM_AUX_DEFER || reg == AUX_RX_COMM_I2C_DEFER) { dev_dbg(dp->dev, "Defer: %d\n\n", reg); @@ -895,7 +908,7 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, } for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { - reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 + 4 * cur_data_idx); edid[i + cur_data_idx] = (unsigned char)reg; } @@ -910,14 +923,14 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) reg = bwtype; if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) - writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); + analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg); } void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); + reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); *bwtype = reg; } @@ -926,14 +939,14 @@ void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) u32 reg; reg = count; - writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); + analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); } void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); + reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); *count = reg; } @@ -943,13 +956,13 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, u32 reg; if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); reg |= ENHANCED; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); reg &= ~ENHANCED; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); } } @@ -961,25 +974,25 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, switch (pattern) { case PRBS7: reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); break; case D10_2: reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); break; case TRAINING_PTN1: reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); break; case TRAINING_PTN2: reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); break; case DP_NONE: reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE | SW_TRAINING_PATTERN_SET_NORMAL; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); break; default: break; @@ -991,10 +1004,10 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg &= ~PRE_EMPHASIS_SET_MASK; reg |= level << PRE_EMPHASIS_SET_SHIFT; - writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, @@ -1002,10 +1015,10 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg &= ~PRE_EMPHASIS_SET_MASK; reg |= level << PRE_EMPHASIS_SET_SHIFT; - writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, @@ -1013,10 +1026,10 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg &= ~PRE_EMPHASIS_SET_MASK; reg |= level << PRE_EMPHASIS_SET_SHIFT; - writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, @@ -1024,10 +1037,10 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg &= ~PRE_EMPHASIS_SET_MASK; reg |= level << PRE_EMPHASIS_SET_SHIFT; - writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, @@ -1036,7 +1049,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, u32 reg; reg = training_lane; - writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, @@ -1045,7 +1058,7 @@ void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, u32 reg; reg = training_lane; - writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, @@ -1054,7 +1067,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, u32 reg; reg = training_lane; - writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL, reg); } void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, @@ -1063,14 +1076,14 @@ void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, u32 reg; reg = training_lane; - writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); + analogix_dp_write(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL, reg); } u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL); return reg; } @@ -1078,7 +1091,7 @@ u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL); return reg; } @@ -1086,7 +1099,7 @@ u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL); return reg; } @@ -1094,7 +1107,7 @@ u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL); return reg; } @@ -1102,15 +1115,15 @@ void analogix_dp_reset_macro(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); + reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); reg |= MACRO_RST; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); + analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); /* 10 us is the minimum reset time. */ udelay(20); reg &= ~MACRO_RST; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); + analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); } void analogix_dp_init_video(struct analogix_dp_device *dp) @@ -1118,19 +1131,19 @@ void analogix_dp_init_video(struct analogix_dp_device *dp) u32 reg; reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; - writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); + analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); reg = 0x0; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); reg = CHA_CRI(4) | CHA_CTRL; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); reg = 0x0; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); reg = VID_HRES_TH(2) | VID_VRES_TH(0); - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); } void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) @@ -1141,34 +1154,34 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | (dp->video_info.color_depth << IN_BPC_SHIFT) | (dp->video_info.color_space << IN_COLOR_F_SHIFT); - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); reg &= ~IN_YC_COEFFI_MASK; if (dp->video_info.ycbcr_coeff) reg |= IN_YC_COEFFI_ITU709; else reg |= IN_YC_COEFFI_ITU601; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); } int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); if (!(reg & DET_STA)) return -EINVAL; - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); if (reg & CHA_STA) return -EINVAL; @@ -1183,30 +1196,30 @@ void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, u32 reg; if (type == REGISTER_M) { - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); reg |= FIX_M_VID; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); reg = m_value & 0xff; - writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); + analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); reg = (m_value >> 8) & 0xff; - writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); + analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); reg = (m_value >> 16) & 0xff; - writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); + analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); reg = n_value & 0xff; - writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); + analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); reg = (n_value >> 8) & 0xff; - writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); + analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); reg = (n_value >> 16) & 0xff; - writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); + analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); reg &= ~FIX_M_VID; - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); - writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); - writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); - writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); + analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); + analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); + analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); } } @@ -1215,13 +1228,13 @@ void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) u32 reg; if (type == VIDEO_TIMING_FROM_CAPTURE) { - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); reg &= ~FORMAT_SEL; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); reg |= FORMAT_SEL; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); } } @@ -1230,15 +1243,15 @@ void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) u32 reg; if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); reg &= ~VIDEO_MODE_MASK; reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; - writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); reg &= ~VIDEO_MODE_MASK; reg |= VIDEO_MODE_SLAVE_MODE; - writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); } } @@ -1246,19 +1259,19 @@ void analogix_dp_start_video(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); reg |= VIDEO_EN; - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); } int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); - writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); + analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); + reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); if (!(reg & STRM_VALID)) return -EINVAL; @@ -1269,44 +1282,44 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); reg |= MASTER_VID_FUNC_EN_N; - writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); + analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); reg &= ~INTERACE_SCAN_CFG; reg |= (dp->video_info.interlaced << 2); - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); reg &= ~VSYNC_POLARITY_CFG; reg |= (dp->video_info.v_sync_polarity << 1); - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); reg &= ~HSYNC_POLARITY_CFG; reg |= (dp->video_info.h_sync_polarity << 0); - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); + analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; - writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); + analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); } void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); reg &= ~SCRAMBLING_DISABLE; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); } void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) { u32 reg; - reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); reg |= SCRAMBLING_DISABLE; - writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); + analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); }