rockchip: rk3568: add irq definitions

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I13b662eff5a86b8fe021612130e50b9c3e783105

include/configs/rk3568_common.h

@@ -27,6 +27,7 @@
 
 #define GICD_BASE			0xfd400000
 #define GICR_BASE			0xfd460000
+#define GICC_BASE			0xfd800000
 
 /* MMC/SD IP block */
 #define CONFIG_BOUNCE_BUFFER
@@ -44,7 +45,7 @@
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00500000\0" \
 	"pxefile_addr_r=0x00600000\0" \
-	"fdt_addr_r=0x01f00000\0" \
+	"fdt_addr_r=0x0a100000\0" \
 	"kernel_addr_no_bl32_r=0x00280000\0" \
 	"kernel_addr_r=0x00680000\0" \
 	"kernel_addr_c=0x04080000\0" \
@@ -58,6 +59,11 @@
 	ROCKCHIP_DEVICE_SETTINGS \
 	RKIMG_DET_BOOTDEV \
 	BOOTENV
+
+#undef RKIMG_BOOTCOMMAND
+#define RKIMG_BOOTCOMMAND		\
+	"boot_fit;"			\
+	"boot_android ${devtype} ${devnum};"
 #endif
 
 /* rockchip ohci host driver */

include/irq-platform.h

@@ -220,6 +220,26 @@
 #define IRQ_GPIO3			69
 #define IRQ_GPIO4			70
 
+#elif defined(CONFIG_ROCKCHIP_RK3568)
+#define GPIO0_PHYS			0xfdd60000
+#define GPIO1_PHYS			0xfe740000
+#define GPIO2_PHYS			0xfe750000
+#define GPIO3_PHYS			0xfe760000
+#define GPIO4_PHYS			0xfe770000
+
+#define GIC_IRQS_NR			(5 * 32)
+#define GPIO_IRQS_NR			(5 * 32)
+
+#define GPIO_BANK_NUM			5
+#define GPIO_BANK_PINS			32
+
+#define IRQ_TIMER0			141
+#define IRQ_GPIO0			65
+#define IRQ_GPIO1			66
+#define IRQ_GPIO2			67
+#define IRQ_GPIO3			68
+#define IRQ_GPIO4			69
+
 #else
 "Missing define RIQ relative things"
 #endif

include/rk_timer_irq.h

@@ -63,6 +63,10 @@
 #elif defined(CONFIG_ROCKCHIP_RV1126)
 #define TIMER_BASE		(0xFF660000 + 0x20)	/* TIMER 1 */
 #define TIMER_IRQ		IRQ_TIMER1
+#elif defined(CONFIG_ROCKCHIP_RK3568)
+/* Only timer0 can wakeup system suspend */
+#define TIMER_BASE		(0xFE5F0000 + 0x00)	/* TIMER 1 */
+#define TIMER_IRQ		IRQ_TIMER0
 #else
 "Missing definitions of timer module test"
 #endif