sound: rockchip: add driver support for rk809/rk817
This patch adds driver support for rockchip rk809/rk817. Change-Id: I0e8355fa6dffb23d8413c0b3a198757aa2d2360c Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
Jianhong Chen
parent
7a5efcbd67
commit
4afb7f9c57
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@ -49,6 +49,13 @@ config SOUND_MAX98095
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audio data and I2C for codec control. At present it only works
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with the Samsung I2S driver.
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config SOUND_RK817
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bool "Support Rockchip rk809/rk817 audio codec"
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depends on I2S_ROCKCHIP && PMIC_RK8XX
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help
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Enable the rk809/rk817 audio codec. This is connected via I2S for
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audio data and I2C for codec control.
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config SOUND_SANDBOX
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bool "Support sandbox emulated audio codec"
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depends on SANDBOX && SOUND
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@ -12,3 +12,4 @@ obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o
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obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o
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obj-$(CONFIG_SOUND_WM8994) += wm8994.o
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obj-$(CONFIG_SOUND_MAX98095) += max98095.o
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obj-$(CONFIG_SOUND_RK817) += rk817_codec.o
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@ -0,0 +1,368 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <power/pmic.h>
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#include <power/rk8xx_pmic.h>
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#include <sound.h>
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#include "rk817_codec.h"
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#define DBG(format, ...) \
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printf("RK817: " format, ## __VA_ARGS__)
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/* For route */
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#define RK817_CODEC_PLAYBACK 1
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#define RK817_CODEC_CAPTURE 2
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#define RK817_CODEC_INCALL 4
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#define RK817_CODEC_ALL (RK817_CODEC_PLAYBACK |\
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RK817_CODEC_CAPTURE | RK817_CODEC_INCALL)
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/*
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* DDAC L/R volume setting
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* 0db~-95db,0.375db/step,for example:
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* 0: 0dB
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* 0x0a: -3.75dB
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* 0x7d: -46dB
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* 0xff: -95dB
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*/
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#define OUT_VOLUME (0x03)
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#define CODEC_SET_SPK 1
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#define CODEC_SET_HP 2
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#define INITIAL_VOLUME 3
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struct rk817_codec_priv {
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struct udevice *dev;
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struct rk8xx_priv *rk817;
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unsigned int stereo_sysclk;
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unsigned int rate;
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unsigned int spk_volume;
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unsigned int hp_volume;
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bool use_ext_amplifier;
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long int playback_path;
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int spk_mute_delay;
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int hp_mute_delay;
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};
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static int snd_soc_write(struct udevice *dev, unsigned int reg,
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unsigned int val)
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{
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return pmic_reg_write(dev, reg, val);
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}
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static int snd_soc_update_bits(struct udevice *dev, unsigned int reg,
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unsigned int mask, unsigned int value)
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{
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return pmic_clrsetbits(dev, reg, mask, value);
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}
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static int rk817_reset(struct rk817_codec_priv *priv)
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{
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struct udevice *codec = priv->dev->parent;
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snd_soc_write(codec, RK817_CODEC_DTOP_LPT_SRST, 0x40);
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snd_soc_write(codec, RK817_CODEC_DDAC_POPD_DACST, 0x02);
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return 0;
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}
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static struct rk817_reg_val_typ playback_power_up_list[] = {
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{RK817_CODEC_AREF_RTCFG1, 0x40},
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{RK817_CODEC_DDAC_POPD_DACST, 0x02},
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{RK817_CODEC_DDAC_SR_LMT0, 0x02},
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/* {RK817_CODEC_DTOP_DIGEN_CLKE, 0x0f}, */
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/* APLL */
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{RK817_CODEC_APLL_CFG0, 0x04},
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{RK817_CODEC_APLL_CFG1, 0x58},
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{RK817_CODEC_APLL_CFG2, 0x2d},
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{RK817_CODEC_APLL_CFG3, 0x0c},
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{RK817_CODEC_APLL_CFG4, 0xa5},
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{RK817_CODEC_APLL_CFG5, 0x00},
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{RK817_CODEC_DI2S_RXCMD_TSD, 0x00},
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{RK817_CODEC_DI2S_RSD, 0x00},
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/* {RK817_CODEC_DI2S_CKM, 0x00}, */
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{RK817_CODEC_DI2S_RXCR1, 0x00},
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{RK817_CODEC_DI2S_RXCMD_TSD, 0x20},
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{RK817_CODEC_DTOP_VUCTIME, 0xf4},
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{RK817_CODEC_DDAC_MUTE_MIXCTL, 0x00},
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{RK817_CODEC_DDAC_VOLL, 0x0a},
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{RK817_CODEC_DDAC_VOLR, 0x0a},
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};
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#define RK817_CODEC_PLAYBACK_POWER_UP_LIST_LEN \
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ARRAY_SIZE(playback_power_up_list)
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static struct rk817_reg_val_typ playback_power_down_list[] = {
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{RK817_CODEC_DDAC_MUTE_MIXCTL, 0x01},
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{RK817_CODEC_ADAC_CFG1, 0x0f},
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/* HP */
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{RK817_CODEC_AHP_CFG0, 0xe0},
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{RK817_CODEC_AHP_CP, 0x09},
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/* SPK */
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{RK817_CODEC_ACLASSD_CFG1, 0x69},
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};
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#define RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN \
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ARRAY_SIZE(playback_power_down_list)
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static int rk817_codec_power_up(struct rk817_codec_priv *rk817, int type)
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{
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struct udevice *codec = rk817->dev->parent;
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int i;
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DBG("%s : power up %s %s %s\n", __func__,
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type & RK817_CODEC_PLAYBACK ? "playback" : "",
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type & RK817_CODEC_CAPTURE ? "capture" : "",
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type & RK817_CODEC_INCALL ? "incall" : "");
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if (type & RK817_CODEC_PLAYBACK) {
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snd_soc_update_bits(codec, RK817_CODEC_DTOP_DIGEN_CLKE,
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DAC_DIG_CLK_MASK, DAC_DIG_CLK_EN);
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for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_UP_LIST_LEN; i++) {
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snd_soc_write(codec, playback_power_up_list[i].reg,
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playback_power_up_list[i].value);
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}
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}
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return 0;
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}
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static int rk817_codec_power_down(struct rk817_codec_priv *rk817, int type)
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{
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struct udevice *codec = rk817->dev->parent;
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int i;
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DBG("%s : power down %s %s %s\n", __func__,
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type & RK817_CODEC_PLAYBACK ? "playback" : "",
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type & RK817_CODEC_CAPTURE ? "capture" : "",
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type & RK817_CODEC_INCALL ? "incall" : "");
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/* mute output for pop noise */
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if ((type & RK817_CODEC_PLAYBACK) ||
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(type & RK817_CODEC_INCALL)) {
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snd_soc_update_bits(codec, RK817_CODEC_DDAC_MUTE_MIXCTL,
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DACMT_ENABLE, DACMT_ENABLE);
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}
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if (type & RK817_CODEC_PLAYBACK) {
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for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN; i++) {
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snd_soc_write(codec, playback_power_down_list[i].reg,
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playback_power_down_list[i].value);
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}
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snd_soc_update_bits(codec, RK817_CODEC_DTOP_DIGEN_CLKE,
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DAC_DIG_CLK_MASK, DAC_DIG_CLK_DIS);
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}
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if (type == RK817_CODEC_ALL) {
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for (i = 0; i < RK817_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN; i++) {
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snd_soc_write(codec, playback_power_down_list[i].reg,
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playback_power_down_list[i].value);
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}
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snd_soc_write(codec, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00);
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snd_soc_write(codec, RK817_CODEC_APLL_CFG5, 0x01);
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snd_soc_write(codec, RK817_CODEC_AREF_RTCFG1, 0x06);
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}
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return 0;
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}
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static int rk817_playback_path_put(struct rk817_codec_priv *rk817, int path)
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{
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struct udevice *codec = rk817->dev->parent;
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long int pre_path;
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if (rk817->playback_path == path) {
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DBG("%s : playback_path is not changed!\n", __func__);
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return 0;
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}
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pre_path = rk817->playback_path;
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rk817->playback_path = path;
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DBG("%s : set playback_path %ld, pre_path %ld\n",
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__func__, rk817->playback_path, pre_path);
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switch (rk817->playback_path) {
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case OFF:
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rk817_codec_power_down(rk817, RK817_CODEC_PLAYBACK);
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break;
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case RCV:
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case SPK_PATH:
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case RING_SPK:
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if (pre_path == OFF)
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rk817_codec_power_up(rk817, RK817_CODEC_PLAYBACK);
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if (!rk817->use_ext_amplifier) {
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/* power on dac ibias/l/r */
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snd_soc_write(codec, RK817_CODEC_ADAC_CFG1,
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PWD_DACBIAS_ON | PWD_DACD_ON |
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PWD_DACL_ON | PWD_DACR_ON);
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/* CLASS D mode */
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snd_soc_write(codec, RK817_CODEC_DDAC_MUTE_MIXCTL, 0x10);
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/* CLASS D enable */
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snd_soc_write(codec, RK817_CODEC_ACLASSD_CFG1, 0xa5);
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/* restart CLASS D, OCPP/N */
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snd_soc_write(codec, RK817_CODEC_ACLASSD_CFG2, 0xc4);
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} else {
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/* HP_CP_EN , CP 2.3V */
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snd_soc_write(codec, RK817_CODEC_AHP_CP, 0x11);
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/* power on HP two stage opamp ,HP amplitude 0db */
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snd_soc_write(codec, RK817_CODEC_AHP_CFG0, 0x80);
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/* power on dac ibias/l/r */
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snd_soc_write(codec, RK817_CODEC_ADAC_CFG1,
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PWD_DACBIAS_ON | PWD_DACD_DOWN |
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PWD_DACL_ON | PWD_DACR_ON);
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snd_soc_update_bits(codec, RK817_CODEC_DDAC_MUTE_MIXCTL,
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DACMT_ENABLE, DACMT_DISABLE);
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}
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snd_soc_write(codec, RK817_CODEC_DDAC_VOLL, rk817->spk_volume);
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snd_soc_write(codec, RK817_CODEC_DDAC_VOLR, rk817->spk_volume);
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break;
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case HP_PATH:
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case HP_NO_MIC:
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case RING_HP:
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case RING_HP_NO_MIC:
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if (pre_path == OFF)
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rk817_codec_power_up(rk817, RK817_CODEC_PLAYBACK);
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/* HP_CP_EN , CP 2.3V */
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snd_soc_write(codec, RK817_CODEC_AHP_CP, 0x11);
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/* power on HP two stage opamp ,HP amplitude 0db */
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snd_soc_write(codec, RK817_CODEC_AHP_CFG0, 0x80);
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/* power on dac ibias/l/r */
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snd_soc_write(codec, RK817_CODEC_ADAC_CFG1,
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PWD_DACBIAS_ON | PWD_DACD_DOWN |
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PWD_DACL_ON | PWD_DACR_ON);
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snd_soc_update_bits(codec, RK817_CODEC_DDAC_MUTE_MIXCTL,
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DACMT_ENABLE, DACMT_DISABLE);
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snd_soc_write(codec, RK817_CODEC_DDAC_VOLL, rk817->hp_volume);
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snd_soc_write(codec, RK817_CODEC_DDAC_VOLR, rk817->hp_volume);
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break;
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case BT:
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break;
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case SPK_HP:
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case RING_SPK_HP:
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if (pre_path == OFF)
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rk817_codec_power_up(rk817, RK817_CODEC_PLAYBACK);
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/* HP_CP_EN , CP 2.3V */
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snd_soc_write(codec, RK817_CODEC_AHP_CP, 0x11);
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/* power on HP two stage opamp ,HP amplitude 0db */
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snd_soc_write(codec, RK817_CODEC_AHP_CFG0, 0x80);
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/* power on dac ibias/l/r */
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snd_soc_write(codec, RK817_CODEC_ADAC_CFG1,
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PWD_DACBIAS_ON | PWD_DACD_ON |
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PWD_DACL_ON | PWD_DACR_ON);
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if (!rk817->use_ext_amplifier) {
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/* CLASS D mode */
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snd_soc_write(codec, RK817_CODEC_DDAC_MUTE_MIXCTL, 0x10);
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/* CLASS D enable */
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snd_soc_write(codec, RK817_CODEC_ACLASSD_CFG1, 0xa5);
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/* restart CLASS D, OCPP/N */
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snd_soc_write(codec, RK817_CODEC_ACLASSD_CFG2, 0xc4);
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}
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snd_soc_write(codec, RK817_CODEC_DDAC_VOLL, rk817->hp_volume);
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snd_soc_write(codec, RK817_CODEC_DDAC_VOLR, rk817->hp_volume);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int rk817_hw_params(struct udevice *dev, unsigned int samplerate,
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unsigned int fmt, unsigned int channels)
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{
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struct rk817_codec_priv *rk817 = dev_get_priv(dev);
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struct udevice *codec = rk817->dev->parent;
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snd_soc_update_bits(codec, RK817_CODEC_DI2S_CKM,
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RK817_I2S_MODE_MASK, RK817_I2S_MODE_SLV);
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snd_soc_write(codec, RK817_CODEC_DI2S_RXCR2, VDW_RX_16BITS);
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snd_soc_write(codec, RK817_CODEC_DI2S_TXCR2, VDW_TX_16BITS);
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return 0;
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}
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static int rk817_digital_mute(struct rk817_codec_priv *rk817, int mute)
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{
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struct udevice *codec = rk817->dev->parent;
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if (mute)
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snd_soc_update_bits(codec, RK817_CODEC_DDAC_MUTE_MIXCTL,
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DACMT_ENABLE, DACMT_ENABLE);
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else
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snd_soc_update_bits(codec, RK817_CODEC_DDAC_MUTE_MIXCTL,
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DACMT_ENABLE, DACMT_DISABLE);
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return 0;
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}
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static int rk817_startup(struct udevice *dev)
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{
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struct rk817_codec_priv *rk817 = dev_get_priv(dev);
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rk817_playback_path_put(rk817, SPK_HP);
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rk817_digital_mute(rk817, 0);
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return 0;
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}
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static const struct snd_soc_dai_ops rk817_codec_ops = {
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.hw_params = rk817_hw_params,
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.startup = rk817_startup,
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};
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static int rk817_codec_probe(struct udevice *dev)
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{
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struct rk8xx_priv *rk817 = dev_get_priv(dev->parent);
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struct rk817_codec_priv *rk817_codec = dev_get_priv(dev);
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if (!rk817) {
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printf("%s : rk817 is null\n", __func__);
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return -EINVAL;
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}
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switch (rk817->variant) {
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case RK809_ID:
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case RK817_ID:
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break;
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default:
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return -EINVAL;
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}
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rk817_codec->dev = dev;
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rk817_codec->hp_volume = INITIAL_VOLUME;
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rk817_codec->spk_volume = INITIAL_VOLUME;
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rk817_codec->playback_path = OFF;
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rk817_reset(rk817_codec);
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return 0;
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}
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static const struct udevice_id rk817_codec_ids[] = {
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{ .compatible = "rockchip,rk817-codec" },
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{ }
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};
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U_BOOT_DRIVER(rk817) = {
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.name = "rk817_codec",
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.id = UCLASS_CODEC,
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.of_match = rk817_codec_ids,
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.probe = rk817_codec_probe,
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.priv_auto_alloc_size = sizeof(struct rk817_codec_priv),
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.ops = &rk817_codec_ops,
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};
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UCLASS_DRIVER(codec) = {
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.id = UCLASS_CODEC,
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.name = "codec",
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};
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@ -0,0 +1,203 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd
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*/
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#ifndef __RK817_CODEC_H__
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#define __RK817_CODEC_H__
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/* codec register */
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#define RK817_CODEC_BASE 0x0000
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#define RK817_CODEC_DTOP_VUCTL (RK817_CODEC_BASE + 0x12)
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#define RK817_CODEC_DTOP_VUCTIME (RK817_CODEC_BASE + 0x13)
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#define RK817_CODEC_DTOP_LPT_SRST (RK817_CODEC_BASE + 0x14)
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#define RK817_CODEC_DTOP_DIGEN_CLKE (RK817_CODEC_BASE + 0x15)
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#define RK817_CODEC_AREF_RTCFG0 (RK817_CODEC_BASE + 0x16)
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#define RK817_CODEC_AREF_RTCFG1 (RK817_CODEC_BASE + 0x17)
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#define RK817_CODEC_AADC_CFG0 (RK817_CODEC_BASE + 0x18)
|
||||
#define RK817_CODEC_AADC_CFG1 (RK817_CODEC_BASE + 0x19)
|
||||
#define RK817_CODEC_DADC_VOLL (RK817_CODEC_BASE + 0x1a)
|
||||
#define RK817_CODEC_DADC_VOLR (RK817_CODEC_BASE + 0x1b)
|
||||
#define RK817_CODEC_DADC_SR_ACL0 (RK817_CODEC_BASE + 0x1e)
|
||||
#define RK817_CODEC_DADC_ALC1 (RK817_CODEC_BASE + 0x1f)
|
||||
#define RK817_CODEC_DADC_ALC2 (RK817_CODEC_BASE + 0x20)
|
||||
#define RK817_CODEC_DADC_NG (RK817_CODEC_BASE + 0x21)
|
||||
#define RK817_CODEC_DADC_HPF (RK817_CODEC_BASE + 0x22)
|
||||
#define RK817_CODEC_DADC_RVOLL (RK817_CODEC_BASE + 0x23)
|
||||
#define RK817_CODEC_DADC_RVOLR (RK817_CODEC_BASE + 0x24)
|
||||
#define RK817_CODEC_AMIC_CFG0 (RK817_CODEC_BASE + 0x27)
|
||||
#define RK817_CODEC_AMIC_CFG1 (RK817_CODEC_BASE + 0x28)
|
||||
#define RK817_CODEC_DMIC_PGA_GAIN (RK817_CODEC_BASE + 0x29)
|
||||
#define RK817_CODEC_DMIC_LMT1 (RK817_CODEC_BASE + 0x2a)
|
||||
#define RK817_CODEC_DMIC_LMT2 (RK817_CODEC_BASE + 0x2b)
|
||||
#define RK817_CODEC_DMIC_NG1 (RK817_CODEC_BASE + 0x2c)
|
||||
#define RK817_CODEC_DMIC_NG2 (RK817_CODEC_BASE + 0x2d)
|
||||
#define RK817_CODEC_ADAC_CFG0 (RK817_CODEC_BASE + 0x2e)
|
||||
#define RK817_CODEC_ADAC_CFG1 (RK817_CODEC_BASE + 0x2f)
|
||||
#define RK817_CODEC_DDAC_POPD_DACST (RK817_CODEC_BASE + 0x30)
|
||||
#define RK817_CODEC_DDAC_VOLL (RK817_CODEC_BASE + 0x31)
|
||||
#define RK817_CODEC_DDAC_VOLR (RK817_CODEC_BASE + 0x32)
|
||||
#define RK817_CODEC_DDAC_SR_LMT0 (RK817_CODEC_BASE + 0x35)
|
||||
#define RK817_CODEC_DDAC_LMT1 (RK817_CODEC_BASE + 0x36)
|
||||
#define RK817_CODEC_DDAC_LMT2 (RK817_CODEC_BASE + 0x37)
|
||||
#define RK817_CODEC_DDAC_MUTE_MIXCTL (RK817_CODEC_BASE + 0x38)
|
||||
#define RK817_CODEC_DDAC_RVOLL (RK817_CODEC_BASE + 0x39)
|
||||
#define RK817_CODEC_DDAC_RVOLR (RK817_CODEC_BASE + 0x3a)
|
||||
#define RK817_CODEC_AHP_ANTI0 (RK817_CODEC_BASE + 0x3b)
|
||||
#define RK817_CODEC_AHP_ANTI1 (RK817_CODEC_BASE + 0x3c)
|
||||
#define RK817_CODEC_AHP_CFG0 (RK817_CODEC_BASE + 0x3d)
|
||||
#define RK817_CODEC_AHP_CFG1 (RK817_CODEC_BASE + 0x3e)
|
||||
#define RK817_CODEC_AHP_CP (RK817_CODEC_BASE + 0x3f)
|
||||
#define RK817_CODEC_ACLASSD_CFG1 (RK817_CODEC_BASE + 0x40)
|
||||
#define RK817_CODEC_ACLASSD_CFG2 (RK817_CODEC_BASE + 0x41)
|
||||
#define RK817_CODEC_APLL_CFG0 (RK817_CODEC_BASE + 0x42)
|
||||
#define RK817_CODEC_APLL_CFG1 (RK817_CODEC_BASE + 0x43)
|
||||
#define RK817_CODEC_APLL_CFG2 (RK817_CODEC_BASE + 0x44)
|
||||
#define RK817_CODEC_APLL_CFG3 (RK817_CODEC_BASE + 0x45)
|
||||
#define RK817_CODEC_APLL_CFG4 (RK817_CODEC_BASE + 0x46)
|
||||
#define RK817_CODEC_APLL_CFG5 (RK817_CODEC_BASE + 0x47)
|
||||
#define RK817_CODEC_DI2S_CKM (RK817_CODEC_BASE + 0x48)
|
||||
#define RK817_CODEC_DI2S_RSD (RK817_CODEC_BASE + 0x49)
|
||||
#define RK817_CODEC_DI2S_RXCR1 (RK817_CODEC_BASE + 0x4a)
|
||||
#define RK817_CODEC_DI2S_RXCR2 (RK817_CODEC_BASE + 0x4b)
|
||||
#define RK817_CODEC_DI2S_RXCMD_TSD (RK817_CODEC_BASE + 0x4c)
|
||||
#define RK817_CODEC_DI2S_TXCR1 (RK817_CODEC_BASE + 0x4d)
|
||||
#define RK817_CODEC_DI2S_TXCR2 (RK817_CODEC_BASE + 0x4e)
|
||||
#define RK817_CODEC_DI2S_TXCR3_TXCMD (RK817_CODEC_BASE + 0x4f)
|
||||
|
||||
/* RK817_CODEC_DTOP_DIGEN_CLKE */
|
||||
#define ADC_DIG_CLK_MASK (0xf << 4)
|
||||
#define ADC_DIG_CLK_SFT 4
|
||||
#define ADC_DIG_CLK_DIS (0x0 << 4)
|
||||
#define ADC_DIG_CLK_EN (0xf << 4)
|
||||
|
||||
#define DAC_DIG_CLK_MASK (0xf << 0)
|
||||
#define DAC_DIG_CLK_SFT 0
|
||||
#define DAC_DIG_CLK_DIS (0x0 << 0)
|
||||
#define DAC_DIG_CLK_EN (0xf << 0)
|
||||
|
||||
/* RK817_CODEC_APLL_CFG5 */
|
||||
#define PLL_PW_DOWN (0x01 << 0)
|
||||
#define PLL_PW_UP (0x00 << 0)
|
||||
|
||||
/* RK817_CODEC_DI2S_CKM */
|
||||
#define PDM_EN_MASK (0x1 << 3)
|
||||
#define PDM_EN_SFT 3
|
||||
#define PDM_EN_DISABLE (0x0 << 3)
|
||||
#define PDM_EN_ENABLE (0x1 << 3)
|
||||
|
||||
#define SCK_EN_ENABLE (0x1 << 2)
|
||||
#define SCK_EN_DISABLE (0x0 << 2)
|
||||
|
||||
#define RK817_I2S_MODE_MASK (0x1 << 0)
|
||||
#define RK817_I2S_MODE_SFT 0
|
||||
#define RK817_I2S_MODE_MST (0x1 << 0)
|
||||
#define RK817_I2S_MODE_SLV (0x0 << 0)
|
||||
|
||||
/* RK817_CODEC_DDAC_MUTE_MIXCTL */
|
||||
#define DACMT_ENABLE (0x1 << 0)
|
||||
#define DACMT_DISABLE (0x0 << 0)
|
||||
|
||||
/* RK817_CODEC_DI2S_RXCR2 */
|
||||
#define VDW_RX_24BITS (0x17)
|
||||
#define VDW_RX_16BITS (0x0f)
|
||||
/* RK817_CODEC_DI2S_TXCR2 */
|
||||
#define VDW_TX_24BITS (0x17)
|
||||
#define VDW_TX_16BITS (0x0f)
|
||||
|
||||
/* RK817_CODEC_AHP_CFG1 */
|
||||
#define HP_ANTIPOP_ENABLE (0x1 << 4)
|
||||
#define HP_ANTIPOP_DISABLE (0x0 << 4)
|
||||
|
||||
/* RK817_CODEC_ADAC_CFG1 */
|
||||
#define PWD_DACBIAS_MASK (0x1 << 3)
|
||||
#define PWD_DACBIAS_SFT 3
|
||||
#define PWD_DACBIAS_DOWN (0x1 << 3)
|
||||
#define PWD_DACBIAS_ON (0x0 << 3)
|
||||
|
||||
#define PWD_DACD_MASK (0x1 << 2)
|
||||
#define PWD_DACD_SFT 2
|
||||
#define PWD_DACD_DOWN (0x1 << 2)
|
||||
#define PWD_DACD_ON (0x0 << 2)
|
||||
|
||||
#define PWD_DACL_MASK (0x1 << 1)
|
||||
#define PWD_DACL_SFT 1
|
||||
#define PWD_DACL_DOWN (0x1 << 1)
|
||||
#define PWD_DACL_ON (0x0 << 1)
|
||||
|
||||
#define PWD_DACR_MASK (0x1 << 0)
|
||||
#define PWD_DACR_SFT 0
|
||||
#define PWD_DACR_DOWN (0x1 << 0)
|
||||
#define PWD_DACR_ON (0x0 << 0)
|
||||
|
||||
/* RK817_CODEC_AADC_CFG0 */
|
||||
#define ADC_L_PWD_MASK (0x1 << 7)
|
||||
#define ADC_L_PWD_SFT 7
|
||||
#define ADC_L_PWD_DIS (0x0 << 7)
|
||||
#define ADC_L_PWD_EN (0x1 << 7)
|
||||
|
||||
#define ADC_R_PWD_MASK (0x1 << 6)
|
||||
#define ADC_R_PWD_SFT 6
|
||||
#define ADC_R_PWD_DIS (0x0 << 6)
|
||||
#define ADC_R_PWD_EN (0x1 << 6)
|
||||
|
||||
/* RK817_CODEC_AMIC_CFG0 */
|
||||
#define MIC_DIFF_MASK (0x1 << 7)
|
||||
#define MIC_DIFF_SFT 7
|
||||
#define MIC_DIFF_DIS (0x0 << 7)
|
||||
#define MIC_DIFF_EN (0x1 << 7)
|
||||
|
||||
#define PWD_PGA_L_MASK (0x1 << 5)
|
||||
#define PWD_PGA_L_SFT 5
|
||||
#define PWD_PGA_L_DIS (0x0 << 5)
|
||||
#define PWD_PGA_L_EN (0x1 << 5)
|
||||
|
||||
#define PWD_PGA_R_MASK (0x1 << 4)
|
||||
#define PWD_PGA_R_SFT 4
|
||||
#define PWD_PGA_R_DIS (0x0 << 4)
|
||||
#define PWD_PGA_R_EN (0x1 << 4)
|
||||
|
||||
enum {
|
||||
RK817_HIFI,
|
||||
RK817_VOICE,
|
||||
};
|
||||
|
||||
enum {
|
||||
RK817_MONO = 1,
|
||||
RK817_STEREO,
|
||||
};
|
||||
|
||||
enum {
|
||||
OFF,
|
||||
RCV,
|
||||
SPK_PATH,
|
||||
HP_PATH,
|
||||
HP_NO_MIC,
|
||||
BT,
|
||||
SPK_HP,
|
||||
RING_SPK,
|
||||
RING_HP,
|
||||
RING_HP_NO_MIC,
|
||||
RING_SPK_HP,
|
||||
};
|
||||
|
||||
enum {
|
||||
MIC_OFF,
|
||||
MAIN_MIC,
|
||||
HANDS_FREE_MIC,
|
||||
BT_SCO_MIC,
|
||||
};
|
||||
|
||||
struct rk817_reg_val_typ {
|
||||
unsigned int reg;
|
||||
unsigned int value;
|
||||
};
|
||||
|
||||
struct rk817_init_bit_typ {
|
||||
unsigned int reg;
|
||||
unsigned int power_bit;
|
||||
unsigned int init_bit;
|
||||
};
|
||||
|
||||
#endif /* __RK817_CODEC_H__ */
|
||||
|
|
@ -31,6 +31,7 @@ enum uclass_id {
|
|||
UCLASS_BLK, /* Block device */
|
||||
UCLASS_CLK, /* Clock source, e.g. used by peripherals */
|
||||
UCLASS_CPU, /* CPU, typically part of an SoC */
|
||||
UCLASS_CODEC, /* audio codec */
|
||||
UCLASS_CROS_EC, /* Chrome OS EC */
|
||||
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
|
||||
UCLASS_DMA, /* Direct Memory Access */
|
||||
|
|
|
|||
Loading…
Reference in New Issue