drm/rockchip: vop: rk312x use win1 to show logo
since kernel set rk312x win1 to show kernel logo, so here sync with kernel config. Signed-off-by: Sandy Huang <hjc@rock-chips.com> Change-Id: I3ed562526cd6f61359bef1567c7f2ea57149435d
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@ -416,27 +416,14 @@ const struct vop_data rk3328_vop = {
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.reg_len = RK3328_DSP_VACT_ST_END_F1 * 4,
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};
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static const struct vop_scl_regs rk3036_win_scl = {
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.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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};
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static const struct vop_win rk3036_win0_data = {
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.scl = &rk3036_win_scl,
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.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
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.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
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.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
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.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
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.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
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.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
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.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
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.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
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.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
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static const struct vop_win rk3126_win1_data = {
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.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
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.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
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.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
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.dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
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};
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static const struct vop_ctrl rk3036_ctrl_data = {
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@ -471,7 +458,7 @@ const struct vop_data rk3036_vop = {
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.version = VOP_VERSION(2, 2),
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.max_output = {1920, 1080},
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.ctrl = &rk3036_ctrl_data,
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.win = &rk3036_win0_data,
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.win = &rk3126_win1_data,
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.line_flag = &rk3036_vop_line_flag,
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.reg_len = RK3036_DSP_VACT_ST_END_F1 * 4,
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};
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@ -876,6 +876,12 @@
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#define RK3036_HWC_LUT_ADDR 0x800
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/* rk3036 register definition end */
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/* rk3126 register definition */
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#define RK3126_WIN1_MST 0x0004c
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#define RK3126_WIN1_DSP_INFO 0x00050
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#define RK3126_WIN1_DSP_ST 0x00054
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/* rk3126 register definition end */
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/* rk3366 register definition */
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#define RK3366_LIT_REG_CFG_DONE 0x00000
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#define RK3366_LIT_VERSION 0x00004
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