arm: rockchip: add RK3308 SOC support
RK3308 is a Soc from Rockchip, which embedded with quad ARM Cortex-A35 and highly integrated audio interfaces. Change-Id: I93958481f2e9f0f8d8c40bbfaaa3899cd82ec43d Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
Kever Yang
parent
178b5aad36
commit
3d78ac3e4e
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@ -0,0 +1,81 @@
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3308_H
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#define _ASM_ARCH_CRU_RK3308_H
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#include <common.h>
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#define MHz 1000000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (816 * MHz)
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#define GPLL_HZ (600 * MHz)
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#define CPLL_HZ (594 * MHz)
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#define CORE_PERI_HZ 204000000
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#define CORE_ACLK_HZ 408000000
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#define BUS_ACLK_HZ 148500000
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#define BUS_HCLK_HZ 148500000
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#define BUS_PCLK_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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enum apll_frequencies {
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APLL_816_MHZ,
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APLL_600_MHZ,
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};
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3308_clk_priv {
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struct rk3308_cru *cru;
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ulong rate;
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};
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struct rk3308_cru {
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struct rk3308_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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} pll[4];
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unsigned int reserved1[8];
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unsigned int mode;
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unsigned int misc;
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unsigned int reserved2[2];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int pll_lock;
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unsigned int reserved3[6];
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unsigned int hwffc_con0;
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unsigned int reserved4;
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unsigned int hwffc_th;
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unsigned int hwffc_intst;
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unsigned int apll_con0_s;
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unsigned int apll_con1_s;
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unsigned int clksel_con0_s;
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unsigned int reserved5;
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unsigned int clksel_con[74];
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unsigned int reserved6[54];
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unsigned int clkgate_con[15];
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unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
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unsigned int ssgtbl[32];
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unsigned int softrst_con[10];
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unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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};
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check_member(rk3308_cru, emmc_con[1], 0x494);
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#endif
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@ -0,0 +1,176 @@
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_rk3308_H
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#define _ASM_ARCH_GRF_rk3308_H
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#include <common.h>
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struct rk3308_grf {
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unsigned int gpio0a_iomux;
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unsigned int reserved0;
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unsigned int gpio0b_iomux;
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unsigned int reserved1;
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unsigned int gpio0c_iomux;
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unsigned int reserved2[3];
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unsigned int gpio1a_iomux;
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unsigned int reserved3;
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unsigned int gpio1bl_iomux;
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unsigned int gpio1bh_iomux;
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unsigned int gpio1cl_iomux;
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unsigned int gpio1ch_iomux;
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unsigned int gpio1d_iomux;
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unsigned int reserved4;
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unsigned int gpio2a_iomux;
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unsigned int reserved5;
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unsigned int gpio2b_iomux;
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unsigned int reserved6;
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unsigned int gpio2c_iomux;
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unsigned int reserved7[3];
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unsigned int gpio3a_iomux;
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unsigned int reserved8;
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unsigned int gpio3b_iomux;
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unsigned int reserved9[5];
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unsigned int gpio4a_iomux;
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unsigned int reserved33;
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unsigned int gpio4b_iomux;
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unsigned int reserved10;
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unsigned int gpio4c_iomux;
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unsigned int reserved11;
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unsigned int gpio4d_iomux;
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unsigned int reserved34;
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unsigned int gpio0a_p;
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unsigned int gpio0b_p;
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unsigned int gpio0c_p;
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unsigned int reserved12;
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unsigned int gpio1a_p;
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unsigned int gpio1b_p;
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unsigned int gpio1c_p;
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unsigned int gpio1d_p;
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unsigned int gpio2a_p;
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unsigned int gpio2b_p;
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unsigned int gpio2c_p;
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unsigned int reserved13;
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unsigned int gpio3a_p;
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unsigned int gpio3b_p;
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unsigned int reserved14[2];
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unsigned int gpio4a_p;
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unsigned int gpio4b_p;
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unsigned int gpio4c_p;
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unsigned int gpio4d_p;
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unsigned int reserved15[(0x100 - 0xec) / 4 - 1];
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unsigned int gpio0a_e;
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unsigned int gpio0b_e;
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unsigned int gpio0c_e;
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unsigned int reserved16;
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unsigned int gpio1a_e;
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unsigned int gpio1b_e;
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unsigned int gpio1c_e;
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unsigned int gpio1d_e;
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unsigned int gpio2a_e;
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unsigned int gpio2b_e;
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unsigned int gpio2c_e;
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unsigned int reserved17;
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unsigned int gpio3a_e;
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unsigned int gpio3b_e;
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unsigned int reserved18[2];
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unsigned int gpio4a_e;
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unsigned int gpio4b_e;
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unsigned int gpio4c_e;
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unsigned int gpio4d_e;
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unsigned int gpio0a_sr;
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unsigned int gpio0b_sr;
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unsigned int gpio0c_sr;
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unsigned int reserved19;
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unsigned int gpio1a_sr;
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unsigned int gpio1b_sr;
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unsigned int gpio1c_sr;
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unsigned int gpio1d_sr;
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unsigned int gpio2a_sr;
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unsigned int gpio2b_sr;
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unsigned int gpio2c_sr;
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unsigned int reserved20;
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unsigned int gpio3a_sr;
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unsigned int gpio3b_sr;
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unsigned int reserved21[2];
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unsigned int gpio4a_sr;
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unsigned int gpio4b_sr;
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unsigned int gpio4c_sr;
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unsigned int gpio4d_sr;
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unsigned int gpio0a_smt;
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unsigned int gpio0b_smt;
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unsigned int gpio0c_smt;
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unsigned int reserved22;
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unsigned int gpio1a_smt;
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unsigned int gpio1b_smt;
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unsigned int gpio1c_smt;
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unsigned int gpio1d_smt;
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unsigned int gpio2a_smt;
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unsigned int gpio2b_smt;
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unsigned int gpio2c_smt;
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unsigned int reserved23;
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unsigned int gpio3a_smt;
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unsigned int gpio3b_smt;
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unsigned int reserved35[2];
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unsigned int gpio4a_smt;
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unsigned int gpio4b_smt;
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unsigned int gpio4c_smt;
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unsigned int gpio4d_smt;
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unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1];
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unsigned int soc_con0;
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unsigned int soc_con1;
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unsigned int soc_con2;
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unsigned int soc_con3;
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unsigned int soc_con4;
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unsigned int soc_con5;
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unsigned int soc_con6;
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unsigned int soc_con7;
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unsigned int soc_con8;
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unsigned int soc_con9;
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unsigned int soc_con10;
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unsigned int reserved25[(0x380 - 0x328) / 4 - 1];
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unsigned int soc_status0;
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unsigned int reserved26[(0x400 - 0x380) / 4 - 1];
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unsigned int cpu_con0;
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unsigned int cpu_con1;
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unsigned int cpu_con2;
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unsigned int reserved27[(0x420 - 0x408) / 4 - 1];
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unsigned int cpu_status0;
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unsigned int cpu_status1;
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unsigned int reserved28[(0x440 - 0x424) / 4 - 1];
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unsigned int pvtm_con0;
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unsigned int pvtm_con1;
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unsigned int pvtm_status0;
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unsigned int pvtm_status1;
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unsigned int reserved29[(0x460 - 0x44C) / 4 - 1];
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unsigned int tsadc_tbl;
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unsigned int tsadc_tbh;
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unsigned int reserved30[(0x480 - 0x464) / 4 - 1];
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unsigned int host0_con0;
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unsigned int host0_con1;
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unsigned int otg_con0;
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unsigned int host0_status0;
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unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1];
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unsigned int mac_con0;
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unsigned int upctrl_con0;
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unsigned int upctrl_status0;
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unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1];
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unsigned int os_reg0;
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unsigned int os_reg1;
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unsigned int os_reg2;
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unsigned int os_reg3;
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unsigned int os_reg4;
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unsigned int os_reg5;
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unsigned int os_reg6;
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unsigned int os_reg7;
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unsigned int os_reg8;
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unsigned int os_reg9;
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unsigned int os_reg10;
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unsigned int os_reg11;
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unsigned int reserved38[(0x800 - 0x52C) / 4 - 1];
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unsigned int chip_id;
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};
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check_member(rk3308_grf, gpio0a_p, 0xa0);
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#endif
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@ -127,6 +127,14 @@ config ROCKCHIP_RK3288
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and video codec support. Peripherals include Gigabit Ethernet,
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3308
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bool "Support Rockchip RK3308"
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select ARM64
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select DEBUG_UART_BOARD_INIT
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help
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The Rockchip RK3308 is a ARM-based Soc which embeded with quad
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Cortex-A35 and highly integrated audio interfaces.
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config ROCKCHIP_RK3328
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config ROCKCHIP_RK3328
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bool "Support Rockchip RK3328"
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bool "Support Rockchip RK3328"
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select ARM64
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select ARM64
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@ -260,6 +268,7 @@ config ROCKCHIP_BOOT_MODE_REG
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default 0x20004040 if ROCKCHIP_RK3188
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default 0x20004040 if ROCKCHIP_RK3188
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default 0x110005c8 if ROCKCHIP_RK322X
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default 0x110005c8 if ROCKCHIP_RK322X
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default 0xff730094 if ROCKCHIP_RK3288
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default 0xff730094 if ROCKCHIP_RK3288
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default 0xff000500 if ROCKCHIP_RK3308
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default 0xff1005c8 if ROCKCHIP_RK3328
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default 0xff1005c8 if ROCKCHIP_RK3328
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default 0xff738200 if ROCKCHIP_RK3368
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default 0xff738200 if ROCKCHIP_RK3368
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default 0xff320300 if ROCKCHIP_RK3399
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default 0xff320300 if ROCKCHIP_RK3399
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@ -41,6 +41,7 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
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endif
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endif
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obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
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obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
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obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
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obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
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obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
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obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
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obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
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obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
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obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
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obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
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obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
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@ -0,0 +1,8 @@
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#
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# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += syscon_rk3308.o
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obj-y += rk3308.o
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@ -0,0 +1,97 @@
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/*
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* Copyright (c) 2018 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/grf_rk3308.h>
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#include <asm/arch/hardware.h>
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#include <asm/armv8/mmu.h>
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#include <debug_uart.h>
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static struct mm_region rk3308_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xff000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xff000000UL,
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.phys = 0xff000000UL,
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.size = 0x01000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3308_mem_map;
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#define GRF_BASE 0xff000000
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enum {
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GPIO1C7_SHIFT = 8,
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GPIO1C7_MASK = GENMASK(11, 8),
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GPIO1C7_GPIO = 0,
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GPIO1C7_UART1_RTSN,
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GPIO1C7_UART2_TX_M0,
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GPIO1C7_SPI2_MOSI,
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GPIO1C7_JTAG_TMS,
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GPIO1C6_SHIFT = 4,
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GPIO1C6_MASK = GENMASK(7, 4),
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GPIO1C6_GPIO = 0,
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GPIO1C6_UART1_CTSN,
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GPIO1C6_UART2_RX_M0,
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GPIO1C6_SPI2_MISO,
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GPIO1C6_JTAG_TCLK,
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GPIO4D3_SHIFT = 6,
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GPIO4D3_MASK = GENMASK(7, 6),
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|
GPIO4D3_GPIO = 0,
|
||||||
|
GPIO4D3_SDMMC_D3,
|
||||||
|
GPIO4D3_UART2_TX_M1,
|
||||||
|
|
||||||
|
GPIO4D2_SHIFT = 4,
|
||||||
|
GPIO4D2_MASK = GENMASK(5, 4),
|
||||||
|
GPIO4D2_GPIO = 0,
|
||||||
|
GPIO4D2_SDMMC_D2,
|
||||||
|
GPIO4D2_UART2_RX_M1,
|
||||||
|
|
||||||
|
UART2_IO_SEL_SHIFT = 2,
|
||||||
|
UART2_IO_SEL_MASK = GENMASK(3, 2),
|
||||||
|
UART2_IO_SEL_M0 = 0,
|
||||||
|
UART2_IO_SEL_M1,
|
||||||
|
UART2_IO_SEL_USB,
|
||||||
|
};
|
||||||
|
|
||||||
|
int arch_cpu_init(void)
|
||||||
|
{
|
||||||
|
debug_uart_init();
|
||||||
|
|
||||||
|
printascii("U-Boot rk3308\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void board_debug_uart_init(void)
|
||||||
|
{
|
||||||
|
static struct rk3308_grf * const grf = (void *)GRF_BASE;
|
||||||
|
|
||||||
|
/* Enable early UART2 channel m1 on the rk3308 */
|
||||||
|
rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
|
||||||
|
UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
|
||||||
|
rk_clrsetreg(&grf->gpio1ch_iomux, GPIO1C7_MASK | GPIO1C6_MASK,
|
||||||
|
GPIO1C7_GPIO << GPIO1C7_SHIFT |
|
||||||
|
GPIO1C6_GPIO << GPIO1C6_SHIFT);
|
||||||
|
rk_clrsetreg(&grf->gpio4d_iomux,
|
||||||
|
GPIO4D3_MASK | GPIO4D2_MASK,
|
||||||
|
GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
|
||||||
|
GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2018 Rockchip Electronics Co., Ltd
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <syscon.h>
|
||||||
|
#include <asm/arch/clock.h>
|
||||||
|
|
||||||
|
static const struct udevice_id rk3308_syscon_ids[] = {
|
||||||
|
{ .compatible = "rockchip,rk3308-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(syscon_rk3308) = {
|
||||||
|
.name = "rk3308_syscon",
|
||||||
|
.id = UCLASS_SYSCON,
|
||||||
|
.of_match = rk3308_syscon_ids,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,67 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_RK3308_COMMON_H
|
||||||
|
#define __CONFIG_RK3308_COMMON_H
|
||||||
|
|
||||||
|
#include "rockchip-common.h"
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
|
||||||
|
#define CONFIG_SYS_CBSIZE 1024
|
||||||
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
|
||||||
|
#define CONFIG_SPL_FRAMEWORK
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NS16550_MEM32
|
||||||
|
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0x00200000
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x00800800
|
||||||
|
#define CONFIG_SPL_STACK 0x00400000
|
||||||
|
#define CONFIG_SPL_TEXT_BASE 0x00000000
|
||||||
|
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||||
|
#define CONFIG_SPL_BSS_START_ADDR 0x2000000
|
||||||
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
|
||||||
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
|
||||||
|
|
||||||
|
#define COUNTER_FREQUENCY 24000000
|
||||||
|
|
||||||
|
#define GICD_BASE 0xff131000
|
||||||
|
#define GICC_BASE 0xff132000
|
||||||
|
|
||||||
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
|
||||||
|
|
||||||
|
/* MMC/SD IP block */
|
||||||
|
#define CONFIG_BOUNCE_BUFFER
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 2
|
||||||
|
#define SDRAM_MAX_SIZE 0xff000000
|
||||||
|
#define SDRAM_BANK_SIZE (2UL << 30)
|
||||||
|
#define CONFIG_PREBOOT
|
||||||
|
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
|
||||||
|
/* usb mass storage */
|
||||||
|
#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||||
|
#define CONFIG_ROCKUSB_G_DNL_PID 0x330d
|
||||||
|
|
||||||
|
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||||
|
"scriptaddr=0x00500000\0" \
|
||||||
|
"pxefile_addr_r=0x00600000\0" \
|
||||||
|
"fdt_addr_r=0x01f00000\0" \
|
||||||
|
"kernel_addr_r=0x02080000\0" \
|
||||||
|
"ramdisk_addr_r=0x04000000\0"
|
||||||
|
|
||||||
|
#include <config_distro_bootcmd.h>
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
ENV_MEM_LAYOUT_SETTINGS \
|
||||||
|
"partitions=" PARTS_DEFAULT \
|
||||||
|
BOOTENV
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue