From 3d78ac3e4e75dad1cfbd93ab65653a424b332b0f Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 25 Feb 2018 17:44:28 +0800 Subject: [PATCH] arm: rockchip: add RK3308 SOC support RK3308 is a Soc from Rockchip, which embedded with quad ARM Cortex-A35 and highly integrated audio interfaces. Change-Id: I93958481f2e9f0f8d8c40bbfaaa3899cd82ec43d Signed-off-by: Andy Yan --- .../include/asm/arch-rockchip/cru_rk3308.h | 81 ++++++++ .../include/asm/arch-rockchip/grf_rk3308.h | 176 ++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 9 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3308/Makefile | 8 + arch/arm/mach-rockchip/rk3308/rk3308.c | 97 ++++++++++ arch/arm/mach-rockchip/rk3308/syscon_rk3308.c | 21 +++ include/configs/rk3308_common.h | 67 +++++++ 8 files changed, 460 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3308.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3308.h create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c create mode 100644 include/configs/rk3308_common.h diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3308.h b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h new file mode 100644 index 0000000000..aeee9cea92 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3308_H +#define _ASM_ARCH_CRU_RK3308_H + +#include + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (816 * MHz) +#define GPLL_HZ (600 * MHz) +#define CPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 204000000 +#define CORE_ACLK_HZ 408000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +enum apll_frequencies { + APLL_816_MHZ, + APLL_600_MHZ, +}; + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3308_clk_priv { + struct rk3308_cru *cru; + ulong rate; +}; + +struct rk3308_cru { + struct rk3308_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; + } pll[4]; + unsigned int reserved1[8]; + unsigned int mode; + unsigned int misc; + unsigned int reserved2[2]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int pll_lock; + unsigned int reserved3[6]; + unsigned int hwffc_con0; + unsigned int reserved4; + unsigned int hwffc_th; + unsigned int hwffc_intst; + unsigned int apll_con0_s; + unsigned int apll_con1_s; + unsigned int clksel_con0_s; + unsigned int reserved5; + unsigned int clksel_con[74]; + unsigned int reserved6[54]; + unsigned int clkgate_con[15]; + unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; + unsigned int ssgtbl[32]; + unsigned int softrst_con[10]; + unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rk3308_cru, emmc_con[1], 0x494); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h new file mode 100644 index 0000000000..7e8e3a62f8 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_rk3308_H +#define _ASM_ARCH_GRF_rk3308_H + +#include + +struct rk3308_grf { + unsigned int gpio0a_iomux; + unsigned int reserved0; + unsigned int gpio0b_iomux; + unsigned int reserved1; + unsigned int gpio0c_iomux; + unsigned int reserved2[3]; + unsigned int gpio1a_iomux; + unsigned int reserved3; + unsigned int gpio1bl_iomux; + unsigned int gpio1bh_iomux; + unsigned int gpio1cl_iomux; + unsigned int gpio1ch_iomux; + unsigned int gpio1d_iomux; + unsigned int reserved4; + unsigned int gpio2a_iomux; + unsigned int reserved5; + unsigned int gpio2b_iomux; + unsigned int reserved6; + unsigned int gpio2c_iomux; + unsigned int reserved7[3]; + unsigned int gpio3a_iomux; + unsigned int reserved8; + unsigned int gpio3b_iomux; + unsigned int reserved9[5]; + unsigned int gpio4a_iomux; + unsigned int reserved33; + unsigned int gpio4b_iomux; + unsigned int reserved10; + unsigned int gpio4c_iomux; + unsigned int reserved11; + unsigned int gpio4d_iomux; + unsigned int reserved34; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int reserved12; + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int reserved13; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int reserved14[2]; + unsigned int gpio4a_p; + unsigned int gpio4b_p; + unsigned int gpio4c_p; + unsigned int gpio4d_p; + unsigned int reserved15[(0x100 - 0xec) / 4 - 1]; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int reserved16; + unsigned int gpio1a_e; + unsigned int gpio1b_e; + unsigned int gpio1c_e; + unsigned int gpio1d_e; + unsigned int gpio2a_e; + unsigned int gpio2b_e; + unsigned int gpio2c_e; + unsigned int reserved17; + unsigned int gpio3a_e; + unsigned int gpio3b_e; + unsigned int reserved18[2]; + unsigned int gpio4a_e; + unsigned int gpio4b_e; + unsigned int gpio4c_e; + unsigned int gpio4d_e; + unsigned int gpio0a_sr; + unsigned int gpio0b_sr; + unsigned int gpio0c_sr; + unsigned int reserved19; + unsigned int gpio1a_sr; + unsigned int gpio1b_sr; + unsigned int gpio1c_sr; + unsigned int gpio1d_sr; + unsigned int gpio2a_sr; + unsigned int gpio2b_sr; + unsigned int gpio2c_sr; + unsigned int reserved20; + unsigned int gpio3a_sr; + unsigned int gpio3b_sr; + unsigned int reserved21[2]; + unsigned int gpio4a_sr; + unsigned int gpio4b_sr; + unsigned int gpio4c_sr; + unsigned int gpio4d_sr; + unsigned int gpio0a_smt; + unsigned int gpio0b_smt; + unsigned int gpio0c_smt; + unsigned int reserved22; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int reserved23; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int reserved35[2]; + unsigned int gpio4a_smt; + unsigned int gpio4b_smt; + unsigned int gpio4c_smt; + unsigned int gpio4d_smt; + unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_con3; + unsigned int soc_con4; + unsigned int soc_con5; + unsigned int soc_con6; + unsigned int soc_con7; + unsigned int soc_con8; + unsigned int soc_con9; + unsigned int soc_con10; + unsigned int reserved25[(0x380 - 0x328) / 4 - 1]; + unsigned int soc_status0; + unsigned int reserved26[(0x400 - 0x380) / 4 - 1]; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int reserved27[(0x420 - 0x408) / 4 - 1]; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int reserved28[(0x440 - 0x424) / 4 - 1]; + unsigned int pvtm_con0; + unsigned int pvtm_con1; + unsigned int pvtm_status0; + unsigned int pvtm_status1; + unsigned int reserved29[(0x460 - 0x44C) / 4 - 1]; + unsigned int tsadc_tbl; + unsigned int tsadc_tbh; + unsigned int reserved30[(0x480 - 0x464) / 4 - 1]; + unsigned int host0_con0; + unsigned int host0_con1; + unsigned int otg_con0; + unsigned int host0_status0; + unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1]; + unsigned int mac_con0; + unsigned int upctrl_con0; + unsigned int upctrl_status0; + unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1]; + unsigned int os_reg0; + unsigned int os_reg1; + unsigned int os_reg2; + unsigned int os_reg3; + unsigned int os_reg4; + unsigned int os_reg5; + unsigned int os_reg6; + unsigned int os_reg7; + unsigned int os_reg8; + unsigned int os_reg9; + unsigned int os_reg10; + unsigned int os_reg11; + unsigned int reserved38[(0x800 - 0x52C) / 4 - 1]; + unsigned int chip_id; +}; +check_member(rk3308_grf, gpio0a_p, 0xa0); +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 74436308a3..74c848757f 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -127,6 +127,14 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3308 + bool "Support Rockchip RK3308" + select ARM64 + select DEBUG_UART_BOARD_INIT + help + The Rockchip RK3308 is a ARM-based Soc which embeded with quad + Cortex-A35 and highly integrated audio interfaces. + config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 @@ -260,6 +268,7 @@ config ROCKCHIP_BOOT_MODE_REG default 0x20004040 if ROCKCHIP_RK3188 default 0x110005c8 if ROCKCHIP_RK322X default 0xff730094 if ROCKCHIP_RK3288 + default 0xff000500 if ROCKCHIP_RK3308 default 0xff1005c8 if ROCKCHIP_RK3328 default 0xff738200 if ROCKCHIP_RK3368 default 0xff320300 if ROCKCHIP_RK3399 diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 4452117a73..de4faf2fa9 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ diff --git a/arch/arm/mach-rockchip/rk3308/Makefile b/arch/arm/mach-rockchip/rk3308/Makefile new file mode 100644 index 0000000000..196774d3e5 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3308/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2018 Rockchip Electronics Co., Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += syscon_rk3308.o +obj-y += rk3308.o diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c new file mode 100644 index 0000000000..3642a861f5 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static struct mm_region rk3308_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xff000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xff000000UL, + .phys = 0xff000000UL, + .size = 0x01000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3308_mem_map; + +#define GRF_BASE 0xff000000 + +enum { + + GPIO1C7_SHIFT = 8, + GPIO1C7_MASK = GENMASK(11, 8), + GPIO1C7_GPIO = 0, + GPIO1C7_UART1_RTSN, + GPIO1C7_UART2_TX_M0, + GPIO1C7_SPI2_MOSI, + GPIO1C7_JTAG_TMS, + + GPIO1C6_SHIFT = 4, + GPIO1C6_MASK = GENMASK(7, 4), + GPIO1C6_GPIO = 0, + GPIO1C6_UART1_CTSN, + GPIO1C6_UART2_RX_M0, + GPIO1C6_SPI2_MISO, + GPIO1C6_JTAG_TCLK, + + GPIO4D3_SHIFT = 6, + GPIO4D3_MASK = GENMASK(7, 6), + GPIO4D3_GPIO = 0, + GPIO4D3_SDMMC_D3, + GPIO4D3_UART2_TX_M1, + + GPIO4D2_SHIFT = 4, + GPIO4D2_MASK = GENMASK(5, 4), + GPIO4D2_GPIO = 0, + GPIO4D2_SDMMC_D2, + GPIO4D2_UART2_RX_M1, + + UART2_IO_SEL_SHIFT = 2, + UART2_IO_SEL_MASK = GENMASK(3, 2), + UART2_IO_SEL_M0 = 0, + UART2_IO_SEL_M1, + UART2_IO_SEL_USB, +}; + +int arch_cpu_init(void) +{ + debug_uart_init(); + + printascii("U-Boot rk3308\n"); + + return 0; +} + +void board_debug_uart_init(void) +{ + static struct rk3308_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART2 channel m1 on the rk3308 */ + rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, + UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT); + rk_clrsetreg(&grf->gpio1ch_iomux, GPIO1C7_MASK | GPIO1C6_MASK, + GPIO1C7_GPIO << GPIO1C7_SHIFT | + GPIO1C6_GPIO << GPIO1C6_SHIFT); + rk_clrsetreg(&grf->gpio4d_iomux, + GPIO4D3_MASK | GPIO4D2_MASK, + GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT | + GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT); +} diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c new file mode 100644 index 0000000000..109fcacd4b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id rk3308_syscon_ids[] = { + { .compatible = "rockchip,rk3308-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3308) = { + .name = "rk3308_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3308_syscon_ids, +}; diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h new file mode 100644 index 0000000000..24bf22cd8e --- /dev/null +++ b/include/configs/rk3308_common.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3308_COMMON_H +#define __CONFIG_RK3308_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SPL_FRAMEWORK + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_TEXT_BASE 0x00000000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define COUNTER_FREQUENCY 24000000 + +#define GICD_BASE 0xff131000 +#define GICC_BASE 0xff132000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 2 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_PREBOOT + +#ifndef CONFIG_SPL_BUILD + +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_ROCKUSB_G_DNL_PID 0x330d + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02080000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif