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rochchip: board: only map op-tee share memory as dcache enabled 

The cache fixup is for the data coherence when communication
between U-Boot and OP-TEE. And data abort exception appeares on
OP-TEE V1 32bit platform due to unknown reason.
So only the share memory need be mapped as dcache enabled.

Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: I92b62ef5fbdf47adc0328a14034a5861e8e77fed
This commit is contained in:
Elon Zhang 2020-08-14 10:59:13 +08:00
parent eee28ceac9
commit 396e3049bd
3 changed files with 22 additions and 3 deletions
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12
arch/arm/mach-rockchip/board.c
View File

@ -35,6 +35,7 @@
#include <power/charge_display.h> #include <power/charge_display.h>
#include <power/regulator.h> #include <power/regulator.h>
#include <optee_include/OpteeClientInterface.h> #include <optee_include/OpteeClientInterface.h>
#include <optee_include/OpteeClientApiLib.h>
#include <optee_include/tee_api_defines.h> #include <optee_include/tee_api_defines.h>
#include <asm/arch/boot_mode.h> #include <asm/arch/boot_mode.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
@ -419,7 +420,7 @@ int board_fdt_fixup(void *blob)
#if defined(CONFIG_ARM64_BOOT_AARCH32) || !defined(CONFIG_ARM64) #if defined(CONFIG_ARM64_BOOT_AARCH32) || !defined(CONFIG_ARM64)
/* /*
* Common for OP-TEE: * Common for OP-TEE:
* 64-bit & 32-bit mode: dcache is always enabled; * 64-bit & 32-bit mode: share memory dcache is always enabled;
* *
* Common for U-Boot: * Common for U-Boot:
* 64-bit mode: MMU table is static defined in rkxxx.c file, all memory * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory
@ -433,16 +434,21 @@ int board_fdt_fixup(void *blob)
* For the data coherence when communication between U-Boot and OP-TEE, U-Boot * For the data coherence when communication between U-Boot and OP-TEE, U-Boot
* should follow OP-TEE MMU policy. * should follow OP-TEE MMU policy.
* *
* So 32-bit mode U-Boot should map OP-TEE memory as dcache enabled. * So 32-bit mode U-Boot should map OP-TEE share memory as dcache enabled.
*/ */
int board_initr_caches_fixup(void) int board_initr_caches_fixup(void)
{ {
#ifdef CONFIG_OPTEE_CLIENT
struct memblock mem; struct memblock mem;
mem = param_parse_optee_mem(); mem.base = 0;
mem.size = 0;
optee_get_shm_config(&mem.base, &mem.size);
if (mem.size) if (mem.size)
mmu_set_region_dcache_behaviour(mem.base, mem.size, mmu_set_region_dcache_behaviour(mem.base, mem.size,
DCACHE_WRITEBACK); DCACHE_WRITEBACK);
#endif
return 0; return 0;
} }
#endif #endif

1
include/optee_include/OpteeClientApiLib.h
View File

@ -11,5 +11,6 @@
#include <optee_include/tee_client_api.h> #include <optee_include/tee_client_api.h>
TEEC_Result OpteeClientApiLibInitialize(void); TEEC_Result OpteeClientApiLibInitialize(void);
void optee_get_shm_config(phys_addr_t *base, phys_size_t *size);
#endif /*_OPTEE_CLIENT_APILIB_H_*/ #endif /*_OPTEE_CLIENT_APILIB_H_*/

12
lib/optee_clientApi/OpteeClientApiLib.c
View File

@ -39,6 +39,18 @@ static bool optee_api_revision_is_compatible(void)
} }
} }
void optee_get_shm_config(phys_addr_t *base, phys_size_t *size)
{
ARM_SMC_ARGS ArmSmcArgs = {0};
ArmSmcArgs.Arg0 = OPTEE_SMC_GET_SHM_CONFIG_V2;
tee_smc_call(&ArmSmcArgs);
*base = ArmSmcArgs.Arg1;
*size = ArmSmcArgs.Arg2;
}
/* /*
* Initlialize the library * Initlialize the library
*/ */