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drivers: ram: rv1126: fix the timing about noc and controller 

1. set the noc ddrtimingc0.b.wrtomwr for LPDDR4
2. set the noc ddrmode.b.mwrsize for LPDDR4
3. update the noc ddrmode.b.burstsize
4. update the controller timing for 328MHz
5. set ddr4timing to 0 except LPDDR4
6. calculate ddr4timing using *_L timing for DDR4

Change-Id: I9f8fae51a05f8547d64da262d4c69fd4edec79fb
Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen 2020-07-22 16:26:34 +08:00 committed by Jianhong Chen
parent a5033de0ca
commit 38b16f0834
29 changed files with 79 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-1056.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000034a},
{0x00000000},
0x000000ff
}
},

4
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-328.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000222},
{0x00000000},
0x000000ff
}
},
@ -33,7 +33,7 @@
{
{
{0x00000000, 0x43041001}, /* MSTR */
{0x00000064, 0x0028003a}, /* RFSHTMG */
{0x00000064, 0x0027003a}, /* RFSHTMG */
{0x000000d0, 0x00020052}, /* INIT0 */
{0x000000d4, 0x00220000}, /* INIT1 */
{0x000000d8, 0x00000100}, /* INIT2 */

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-396.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000222},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-528.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000032a},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-664.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000232},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-784.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000033a},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr3-detect-924.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000342},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-1056.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000033a},
{0x0000034b},
0x000000ff
}
},

4
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-328.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000022a},
{0x00000232},
0x000000ff
}
},
@ -33,7 +33,7 @@
{
{
{0x00000000, 0x43049010}, /* MSTR */
{0x00000064, 0x0028003a}, /* RFSHTMG */
{0x00000064, 0x0027003a}, /* RFSHTMG */
{0x000000d0, 0x00020052}, /* INIT0 */
{0x000000d4, 0x00220000}, /* INIT1 */
{0x000000d8, 0x00000100}, /* INIT2 */

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-396.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000022a},
{0x00000232},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-528.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000022a},
{0x00000232},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-664.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000022a},
{0x0000023a},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-784.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000022a},
{0x0000033a},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-ddr4-detect-924.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000232},
{0x00000342},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-1056.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000542},
{0x00000000},
0x000000ff
}
},

4
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-328.inc
View File

@ -15,11 +15,11 @@
},
{
{0x290a060a},
{0x08020303},
{0x08020403},
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000021a},
{0x00000000},
0x000000ff
}
},

4
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-396.inc
View File

@ -15,11 +15,11 @@
},
{
{0x2b0d080d},
{0x0a020303},
{0x0a020403},
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000021a},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-528.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000322},
{0x00000000},
0x000000ff
}
},

4
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-664.inc
View File

@ -15,11 +15,11 @@
},
{
{0x32150d15},
{0x11030504},
{0x11030604},
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000032a},
{0x00000000},
0x000000ff
}
},

2
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-784.inc
View File

@ -19,7 +19,7 @@
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000432},
{0x00000000},
0x000000ff
}
},

4
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-924.inc
View File

@ -15,11 +15,11 @@
},
{
{0x391d141d},
{0x17050706},
{0x17050806},
{0x00000002},
{0x00001111},
{0x0000000c},
{0x0000053a},
{0x00000000},
0x000000ff
}
},

8
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-1056.inc
View File

@ -15,11 +15,11 @@
},
{
{0x41241522},
{0x15050a07},
{0x00000002},
{0x15050b07},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000554},
{0x00000054},
{0x00000000},
0x000000ff
}
},

12
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-328.inc
View File

@ -16,10 +16,10 @@
{
{0x2f0d060a},
{0x07020804},
{0x00000002},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000244},
{0x00000054},
{0x00000000},
0x000000ff
}
},
@ -33,8 +33,8 @@
{
{
{0x00000000, 0x81081020}, /* MSTR */
{0x00000064, 0x0014002f}, /* RFSHTMG */
{0x000000d0, 0x00020144}, /* INIT0 */
{0x00000064, 0x0014002e}, /* RFSHTMG */
{0x000000d0, 0x00020142}, /* INIT0 */
{0x000000d4, 0x00220000}, /* INIT1 */
{0x000000d8, 0x00000202}, /* INIT2 */
{0x000000dc, 0x00240012}, /* INIT3 */
@ -54,7 +54,7 @@
{0x00000130, 0x00020000}, /* DRAMTMG12 */
{0x00000134, 0x00100002}, /* DRAMTMG13 */
{0x00000138, 0x00000030}, /* DRAMTMG14 */
{0x00000180, 0x00a500a5}, /* ZQCTL0 */
{0x00000180, 0x00a400a4}, /* ZQCTL0 */
{0x00000184, 0x00900000}, /* ZQCTL1 */
{0x00000190, 0x07040000}, /* DFITMG0 */
{0x00000198, 0x07000101}, /* DFILPCFG0 */

6
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-396.inc
View File

@ -16,10 +16,10 @@
{
{0x3110080d},
{0x08020804},
{0x00000002},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000244},
{0x00000054},
{0x00000000},
0x000000ff
}
},

6
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-528.inc
View File

@ -16,10 +16,10 @@
{
{0x34140b11},
{0x0b030804},
{0x00000002},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000344},
{0x00000054},
{0x00000000},
0x000000ff
}
},

6
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-664.inc
View File

@ -16,10 +16,10 @@
{
{0x36170d15},
{0x0d030805},
{0x00000002},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000344},
{0x00000054},
{0x00000000},
0x000000ff
}
},

6
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-784.inc
View File

@ -16,10 +16,10 @@
{
{0x391b1019},
{0x10040805},
{0x00000002},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000444},
{0x00000054},
{0x00000000},
0x000000ff
}
},

6
drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-924.inc
View File

@ -16,10 +16,10 @@
{
{0x3e20121d},
{0x12050a07},
{0x00000002},
{0x00000602},
{0x00001111},
{0x0000000c},
{0x00000554},
{0x00000054},
{0x00000000},
0x000000ff
}
},

27
drivers/ram/rockchip/sdram_rv1126.c
View File

@ -1997,6 +1997,32 @@ static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
static void update_noc_timing(struct dram_info *dram,
struct rv1126_sdram_params *sdram_params)
{
void __iomem *pctl_base = dram->pctl;
u32 bw, bl;
bw = 8 << sdram_params->ch.cap_info.bw;
bl = ((readl(pctl_base + DDR_PCTL2_MSTR) >> 16) & 0xf) * 2;
/* update the noc timing related to data bus width */
if ((bw / 8 * bl) == 16)
sdram_params->ch.noc_timings.ddrmode.b.burstsize = 0;
else if ((bw / 8 * bl) == 32)
sdram_params->ch.noc_timings.ddrmode.b.burstsize = 1;
else if ((bw / 8 * bl) == 64)
sdram_params->ch.noc_timings.ddrmode.b.burstsize = 2;
else
sdram_params->ch.noc_timings.ddrmode.b.burstsize = 3;
sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty =
(bw == 32) ? 2 : ((bw == 16) ? 4 : 8);
if (sdram_params->base.dramtype == LPDDR4) {
sdram_params->ch.noc_timings.ddrmode.b.mwrsize =
(bw == 16) ? 0x1 : 0x2;
sdram_params->ch.noc_timings.ddrtimingc0.b.wrtomwr =
3 * sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty;
}
writel(sdram_params->ch.noc_timings.ddrtiminga0.d32,
&dram->msch->ddrtiminga0);
writel(sdram_params->ch.noc_timings.ddrtimingb0.d32,
@ -2772,6 +2798,7 @@ void ddr_set_rate(struct dram_info *dram,
lp_stat = low_power_update(dram, 0);
sdram_params_new = get_default_sdram_config(freq);
sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank;
sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw;
pre_set_rate(dram, sdram_params_new, dst_fsp, dst_fsp_lp4);