From 33a03efd7a8193e51a2e10c88cd026a204b25050 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 9 Apr 2019 17:36:21 +0800 Subject: [PATCH] clk: rockchip: rk3128: support pclk_wdt get rate Change-Id: Ie5dbfe5bd3fdd7868a5db64b96471a5524bde462 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk_rk3128.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index 493a0a01c7..edfdcef1c4 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -237,6 +237,7 @@ static ulong rk3128_peri_get_clk(struct rk3128_clk_priv *priv, ulong clk_id) case PCLK_I2C2: case PCLK_I2C3: case PCLK_PWM: + case PCLK_WDT: con = readl(&cru->cru_clksel_con[10]); div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT; parent = rk3128_peri_get_clk(priv, ACLK_PERI); @@ -503,6 +504,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk) case PCLK_I2C2: case PCLK_I2C3: case PCLK_PWM: + case PCLK_WDT: rate = rk3128_peri_get_clk(priv, clk->id); break; case ACLK_CPU: