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net: gmac_rockchip: Add rk3568 gmac support 

Change-Id: I3de9899a27160f5acccc04cd1ac03b406e4b3296
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu 2020-12-17 20:01:53 +08:00 committed by Jianhong Chen
parent befcb6277d
commit 33a014bdc9
2 changed files with 90 additions and 1 deletions
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89
drivers/net/gmac_rockchip.c
View File

@ -16,6 +16,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#ifdef CONFIG_DWC_ETH_QOS
#include <asm/arch/grf_rk3568.h>
#include <asm/arch/grf_rv1126.h>
#include "dwc_eth_qos.h"
#else
@ -57,6 +58,7 @@ struct gmac_rockchip_platdata {
bool clock_input;
int tx_delay;
int rx_delay;
int bus_id;
};
struct rk_gmac_ops {
@ -439,7 +441,8 @@ static int rv1126_set_rgmii_speed(struct rockchip_eth_dev *dev)
ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed",
&clk_speed);
if (ret) {
printf("%s~(ret=%d):\n", __func__, ret);
printf("%s can't get clk_mac_speed clock (ret=%d):\n",
__func__, ret);
return ret;
}
@ -723,6 +726,81 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
RV1108_GMAC_PHY_INTF_SEL_RMII);
}
#else
static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3568_grf *grf;
void *con1;
enum {
RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4,
RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
RK3568_GMAC_PHY_INTF_SEL_RMII = BIT(6),
};
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (pdata->bus_id == 1)
con1 = &grf->mac1_con1;
else
con1 = &grf->mac0_con1;
rk_clrsetreg(con1,
RK3568_GMAC_PHY_INTF_SEL_MASK,
RK3568_GMAC_PHY_INTF_SEL_RMII);
}
static void rk3568_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3568_grf *grf;
void *con0, *con1;
enum {
RK3568_GMAC_PHY_INTF_SEL_SHIFT = 4,
RK3568_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
RK3568_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
RK3568_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
RK3568_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
RK3568_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
RK3568_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
RK3568_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
RK3568_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
};
enum {
RK3568_CLK_RX_DL_CFG_GMAC_SHIFT = 0x8,
RK3568_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(15, 8),
RK3568_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
RK3568_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(7, 0),
};
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (pdata->bus_id == 1) {
con0 = &grf->mac1_con0;
con1 = &grf->mac1_con1;
} else {
con0 = &grf->mac0_con0;
con1 = &grf->mac0_con1;
}
rk_clrsetreg(con0,
RK3568_CLK_RX_DL_CFG_GMAC_MASK |
RK3568_CLK_TX_DL_CFG_GMAC_MASK,
pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT);
rk_clrsetreg(con1,
RK3568_TXCLK_DLY_ENA_GMAC_MASK |
RK3568_RXCLK_DLY_ENA_GMAC_MASK |
RK3568_GMAC_PHY_INTF_SEL_MASK,
RK3568_TXCLK_DLY_ENA_GMAC_ENABLE |
RK3568_RXCLK_DLY_ENA_GMAC_ENABLE |
RK3568_GMAC_PHY_INTF_SEL_RGMII);
}
static void rv1126_set_to_rmii(struct gmac_rockchip_platdata *pdata)
{
struct rv1126_grf *grf;
@ -832,6 +910,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
dw_pdata = &pdata->dw_eth_pdata;
eth_pdata = &dw_pdata->eth_pdata;
#endif
pdata->bus_id = dev->seq;
/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
ret = clk_set_defaults(dev);
if (ret)
@ -1029,6 +1108,12 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
.set_to_rmii = rv1108_gmac_set_to_rmii,
};
#else
const struct rk_gmac_ops rk3568_gmac_ops = {
.fix_mac_speed = rv1126_set_rgmii_speed,
.set_to_rgmii = rk3568_set_to_rgmii,
.set_to_rmii = rk3568_set_to_rmii,
};
const struct rk_gmac_ops rv1126_gmac_ops = {
.fix_mac_speed = rv1126_set_rgmii_speed,
.set_to_rgmii = rv1126_set_to_rgmii,
@ -1057,6 +1142,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,rv1108-gmac",
.data = (ulong)&rv1108_gmac_ops },
#else
{ .compatible = "rockchip,rk3568-gmac",
.data = (ulong)&rk3568_gmac_ops },
{ .compatible = "rockchip,rv1126-gmac",
.data = (ulong)&rv1126_gmac_ops },
#endif

2
include/configs/rk3568_common.h
View File

@ -54,6 +54,8 @@
#define SDRAM_MAX_SIZE 0xf0000000
#define CONFIG_PREBOOT
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#ifndef CONFIG_SPL_BUILD
/* usb mass storage */
#define CONFIG_USB_FUNCTION_MASS_STORAGE