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rockchip: rk3568: Modify fspi pins property 

Change-Id: Icc50a2087cde8a716b306e90ba4c3793883e684c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin 2020-12-02 13:01:44 +08:00
parent 70d0725693
commit 32b04d78e7
1 changed files with 12 additions and 0 deletions
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12
arch/arm/mach-rockchip/rk3568/rk3568.c
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@ -8,6 +8,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rk3568.h>
#include <asm/arch/rk_atags.h>
DECLARE_GLOBAL_DATA_PTR;
@ -19,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_GPIO1C_DS_1 0x224
#define GRF_GPIO1C_DS_2 0x228
#define GRF_GPIO1C_DS_3 0x22c
#define GRF_GPIO1D_DS_0 0x230
#define GRF_GPIO1D_DS_1 0x234
#define GRF_SOC_CON4 0x510
#define EDP_PHY_GRF_BASE 0xfdcb0000
#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
@ -745,6 +748,15 @@ int arch_cpu_init(void)
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
#ifndef CONFIG_TPL_BUILD
/* set the fspi d0 cs0 to level 1 */
if (get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NOR ||
get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NAND) {
writel(0x3f000300, GRF_BASE + GRF_GPIO1D_DS_0);
writel(0x3f000300, GRF_BASE + GRF_GPIO1D_DS_1);
}
#endif
/* Disable eDP phy by default */
writel(0x00070007, EDP_PHY_GRF_CON10);
writel(0x0ff10ff1, EDP_PHY_GRF_CON0);