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UPSTREAM: spi: dw: invert wait condition in dw_spi_xfer 

While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.

Fix that by inverting exit condition for readl_poll_timeout.

Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")

Change-Id: I741ce99a6b6cf57c248426549c0047d636d9e43e
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9b14ac5cc2294ac3eaae92421abff27ed3e6caae)
This commit is contained in:
Eugeniy Paltsev 2018-04-19 17:47:41 +03:00 committed by Kever Yang
parent 7f3cd1e4f8
commit 300e61c1ec
1 changed files with 1 additions and 1 deletions
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2
drivers/spi/designware_spi.c
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@ -425,7 +425,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
* in the beginning of new transfer.
*/
if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
!(val & SR_TF_EMPT) || (val & SR_BUSY),
(val & SR_TF_EMPT) && !(val & SR_BUSY),
RX_TIMEOUT * 1000)) {
ret = -ETIMEDOUT;
}