qiurui
/
rv1126-uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: rockchip: rk322x: print arm enter and init rate 

Change-Id: Iab7034c8cef09908a99b5a1e396f6e015da350fb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-01-22 17:20:30 +08:00 committed by Jianhong Chen
parent 093fdd9f5d
commit 2401c256ec
2 changed files with 34 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/include/asm/arch-rockchip/cru_rk322x.h
View File

@ -21,6 +21,11 @@ struct rk322x_clk_priv {
struct rk322x_cru *cru; struct rk322x_cru *cru;
ulong gpll_hz; ulong gpll_hz;
ulong cpll_hz; ulong cpll_hz;
ulong armclk_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
}; };
struct rk322x_cru { struct rk322x_cru {

38
drivers/clk/rockchip/clk_rk322x.c
View File

@ -608,7 +608,7 @@ static ulong rk322x_clk_get_rate(struct clk *clk)
static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
{ {
struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
ulong ret; ulong ret = 0;
switch (clk->id) { switch (clk->id) {
case PLL_APLL: case PLL_APLL:
@ -627,7 +627,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
priv->gpll_hz = rate; priv->gpll_hz = rate;
break; break;
case ARMCLK: case ARMCLK:
ret = rk322x_armclk_set_clk(priv, rate); if (priv->armclk_hz)
ret = rk322x_armclk_set_clk(priv, rate);
priv->armclk_hz = rate;
break; break;
case HCLK_EMMC: case HCLK_EMMC:
case SCLK_EMMC: case SCLK_EMMC:
@ -982,10 +984,21 @@ static int rk322x_clk_probe(struct udevice *dev)
struct rk322x_clk_priv *priv = dev_get_priv(dev); struct rk322x_clk_priv *priv = dev_get_priv(dev);
int ret = 0; int ret = 0;
priv->sync_kernel = false;
if (!priv->armclk_enter_hz)
priv->armclk_enter_hz =
rockchip_pll_get_rate(&rk322x_pll_clks[APLL],
priv->cru, APLL);
rkclk_init(priv); rkclk_init(priv);
if (!priv->armclk_init_hz)
priv->armclk_init_hz =
rockchip_pll_get_rate(&rk322x_pll_clks[APLL],
priv->cru, APLL);
ret = clk_set_defaults(dev); ret = clk_set_defaults(dev);
if (ret) if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret); debug("%s clk_set_defaults failed %d\n", __func__, ret);
else
priv->sync_kernel = true;
#endif #endif
return 0; return 0;
} }
@ -1052,6 +1065,7 @@ U_BOOT_DRIVER(rockchip_rk322x_cru) = {
int soc_clk_dump(void) int soc_clk_dump(void)
{ {
struct udevice *cru_dev; struct udevice *cru_dev;
struct rk322x_clk_priv *priv;
const struct rk322x_clk_info *clk_dump; const struct rk322x_clk_info *clk_dump;
struct clk clk; struct clk clk;
unsigned long clk_count = ARRAY_SIZE(clks_dump); unsigned long clk_count = ARRAY_SIZE(clks_dump);
@ -1066,7 +1080,13 @@ int soc_clk_dump(void)
return ret; return ret;
} }
printf("CLK:"); priv = dev_get_priv(cru_dev);
printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
priv->sync_kernel ? "sync kernel" : "uboot",
priv->armclk_enter_hz / 1000,
priv->armclk_init_hz / 1000,
priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
priv->set_armclk_rate ? " KHz" : "N/A");
for (i = 0; i < clk_count; i++) { for (i = 0; i < clk_count; i++) {
clk_dump = &clks_dump[i]; clk_dump = &clks_dump[i];
if (clk_dump->name) { if (clk_dump->name) {
@ -1080,18 +1100,18 @@ int soc_clk_dump(void)
clk_free(&clk); clk_free(&clk);
if (i == 0) { if (i == 0) {
if (rate < 0) if (rate < 0)
printf("%10s%20s\n", clk_dump->name, printf(" %s %s\n", clk_dump->name,
"unknown"); "unknown");
else else
printf("%10s%20lu Hz\n", clk_dump->name, printf(" %s %lu KHz\n", clk_dump->name,
rate); rate / 1000);
} else { } else {
if (rate < 0) if (rate < 0)
printf("%14s%20s\n", clk_dump->name, printf(" %s %s\n", clk_dump->name,
"unknown"); "unknown");
else else
printf("%14s%20lu Hz\n", clk_dump->name, printf(" %s %lu KHz\n", clk_dump->name,
rate); rate / 1000);
} }
} }
} }