net: dwc_eth_qos: Export common struct and interface at head file
Open structure data and interface, so that Soc using dw_eth_qos controller can reference. Signed-off-by: David Wu <david.wu@rock-chips.com> Change-Id: Ic845d330465c1bb8f7868fb188e5bf30c865b9b5
This commit is contained in:
David Wu
Joseph Chen
parent
e2d5843168
commit
23ca6f743c
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@ -45,6 +45,7 @@
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/sys_proto.h>
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#endif
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#include "dwc_eth_qos.h"
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/* Core registers */
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@ -99,9 +100,6 @@ struct eqos_mac_regs {
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
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#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
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#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
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@ -122,8 +120,6 @@ struct eqos_mac_regs {
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#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
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#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
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#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
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#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
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#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
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#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
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#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
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#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
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@ -276,65 +272,6 @@ struct eqos_desc {
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#define EQOS_DESC3_LD BIT(28)
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#define EQOS_DESC3_BUF1V BIT(24)
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struct eqos_config {
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bool reg_access_always_ok;
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int mdio_wait;
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int swr_wait;
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int config_mac;
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int config_mac_mdio;
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struct eqos_ops *ops;
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};
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struct eqos_ops {
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void (*eqos_inval_desc)(void *desc);
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void (*eqos_flush_desc)(void *desc);
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void (*eqos_inval_buffer)(void *buf, size_t size);
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void (*eqos_flush_buffer)(void *buf, size_t size);
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int (*eqos_probe_resources)(struct udevice *dev);
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int (*eqos_remove_resources)(struct udevice *dev);
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int (*eqos_stop_resets)(struct udevice *dev);
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int (*eqos_start_resets)(struct udevice *dev);
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void (*eqos_stop_clks)(struct udevice *dev);
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int (*eqos_start_clks)(struct udevice *dev);
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int (*eqos_calibrate_pads)(struct udevice *dev);
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int (*eqos_disable_calibration)(struct udevice *dev);
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int (*eqos_set_tx_clk_speed)(struct udevice *dev);
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ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
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phy_interface_t (*eqos_get_interface)(struct udevice *dev);
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};
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struct eqos_priv {
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struct udevice *dev;
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const struct eqos_config *config;
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fdt_addr_t regs;
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struct eqos_mac_regs *mac_regs;
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struct eqos_mtl_regs *mtl_regs;
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struct eqos_dma_regs *dma_regs;
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struct eqos_tegra186_regs *tegra186_regs;
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struct reset_ctl reset_ctl;
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struct gpio_desc phy_reset_gpio;
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u32 reset_delays[3];
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struct clk clk_master_bus;
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struct clk clk_rx;
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struct clk clk_ptp_ref;
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struct clk clk_tx;
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struct clk clk_ck;
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struct clk clk_slave_bus;
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struct mii_dev *mii;
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struct phy_device *phy;
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int phyaddr;
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u32 max_speed;
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void *descs;
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struct eqos_desc *tx_descs;
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struct eqos_desc *rx_descs;
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int tx_desc_idx, rx_desc_idx;
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void *tx_dma_buf;
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void *rx_dma_buf;
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void *rx_pkt;
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bool started;
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bool reg_access_ok;
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};
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/*
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* TX and RX descriptors are 16 bytes. This causes problems with the cache
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* maintenance on CPUs where the cache-line size exceeds the size of these
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@ -1120,7 +1057,7 @@ static int eqos_adjust_link(struct udevice *dev)
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return 0;
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}
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static int eqos_write_hwaddr(struct udevice *dev)
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int eqos_write_hwaddr(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_platdata(dev);
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struct eqos_priv *eqos = dev_get_priv(dev);
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@ -1174,7 +1111,7 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
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return !is_valid_ethaddr(pdata->enetaddr);
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}
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static int eqos_init(struct udevice *dev)
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int eqos_init(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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@ -1285,7 +1222,7 @@ err:
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return ret;
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}
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static void eqos_enable(struct udevice *dev)
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void eqos_enable(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
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@ -1529,7 +1466,7 @@ static int eqos_start(struct udevice *dev)
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return 0;
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}
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static void eqos_stop(struct udevice *dev)
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void eqos_stop(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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int i;
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@ -1584,7 +1521,7 @@ static void eqos_stop(struct udevice *dev)
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debug("%s: OK\n", __func__);
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}
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static int eqos_send(struct udevice *dev, void *packet, int length)
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int eqos_send(struct udevice *dev, void *packet, int length)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eqos_desc *tx_desc;
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@ -1626,7 +1563,7 @@ static int eqos_send(struct udevice *dev, void *packet, int length)
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return -ETIMEDOUT;
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}
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static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
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int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eqos_desc *rx_desc;
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@ -1651,7 +1588,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
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return length;
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}
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static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
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int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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uchar *packet_expected;
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@ -2030,7 +1967,7 @@ static int eqos_remove_resources_imx(struct udevice *dev)
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return 0;
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}
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static int eqos_probe(struct udevice *dev)
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int eqos_probe(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020
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*/
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#ifndef _DWC_ETH_QOS_H
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#define _DWC_ETH_QOS_H
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#include <reset.h>
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
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#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
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#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
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struct eqos_config {
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bool reg_access_always_ok;
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int mdio_wait;
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int swr_wait;
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int config_mac;
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int config_mac_mdio;
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struct eqos_ops *ops;
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};
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struct eqos_ops {
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void (*eqos_inval_desc)(void *desc);
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void (*eqos_flush_desc)(void *desc);
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void (*eqos_inval_buffer)(void *buf, size_t size);
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void (*eqos_flush_buffer)(void *buf, size_t size);
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int (*eqos_probe_resources)(struct udevice *dev);
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int (*eqos_remove_resources)(struct udevice *dev);
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int (*eqos_stop_resets)(struct udevice *dev);
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int (*eqos_start_resets)(struct udevice *dev);
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void (*eqos_stop_clks)(struct udevice *dev);
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int (*eqos_start_clks)(struct udevice *dev);
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int (*eqos_calibrate_pads)(struct udevice *dev);
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int (*eqos_disable_calibration)(struct udevice *dev);
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int (*eqos_set_tx_clk_speed)(struct udevice *dev);
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ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
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phy_interface_t (*eqos_get_interface)(struct udevice *dev);
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};
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struct eqos_priv {
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struct udevice *dev;
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const struct eqos_config *config;
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fdt_addr_t regs;
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struct eqos_mac_regs *mac_regs;
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struct eqos_mtl_regs *mtl_regs;
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struct eqos_dma_regs *dma_regs;
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struct eqos_tegra186_regs *tegra186_regs;
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struct reset_ctl reset_ctl;
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struct gpio_desc phy_reset_gpio;
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u32 reset_delays[3];
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struct clk clk_master_bus;
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struct clk clk_rx;
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struct clk clk_ptp_ref;
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struct clk clk_tx;
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struct clk clk_ck;
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struct clk clk_slave_bus;
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struct mii_dev *mii;
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struct phy_device *phy;
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int phyaddr;
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u32 max_speed;
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void *descs;
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struct eqos_desc *tx_descs;
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struct eqos_desc *rx_descs;
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int tx_desc_idx, rx_desc_idx;
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void *tx_dma_buf;
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void *rx_dma_buf;
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void *rx_pkt;
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bool started;
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bool reg_access_ok;
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};
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int eqos_init(struct udevice *dev);
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void eqos_enable(struct udevice *dev);
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int eqos_probe(struct udevice *dev);
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void eqos_stop(struct udevice *dev);
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int eqos_send(struct udevice *dev, void *packet, int length);
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int eqos_recv(struct udevice *dev, int flags, uchar **packetp);
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int eqos_free_pkt(struct udevice *dev, uchar *packet, int length);
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int eqos_write_hwaddr(struct udevice *dev);
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#endif
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