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rockchip: rk3308: enlarge CONFIG_SPL_MAX_SIZE to 0x40000 

We are using DRAM offset 0~0x40000 as SPL text size, Note that BSS,
STACK and MALLOC may using separate space.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I19b5f868e8a596a627011ad127a9d34837a6c1b6
This commit is contained in:
Jason Zhu 2020-06-08 19:54:26 +08:00 committed by Jianhong Chen
parent 2e93c98a37
commit 2206b10747
1 changed files with 1 additions and 1 deletions
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2
include/configs/rk3308_common.h
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@ -19,7 +19,7 @@
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x00000000 #define CONFIG_SPL_TEXT_BASE 0x00000000
#define CONFIG_SPL_MAX_SIZE 0x20000 #define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000 #define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000