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rockchip: dts: rv1126: add "data-cached" property 

RV1126 decompress module access data without dcache.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Iee3eb077912e1222fcceab4615f872706cd3d43f
This commit is contained in:
Joseph Chen 2020-06-30 17:31:35 +08:00 committed by Jianhong Chen
parent 8b225c61c2
commit 1aaaf7ac0f
1 changed files with 1 additions and 0 deletions
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arch/arm/dts/rv1126.dtsi
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@ -1317,6 +1317,7 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
clock-names = "aclk", "dclk", "pclk";
data-cached = <0>;
status = "disabled";
};