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rockchip: update CONFIG_SPL_MAX_SIZE to 0x40000 

We are using DRAM offset 0~0x40000 as SPL text size, Note that BSS,
STACK and MALLOC may using separate space.

Change-Id: I1d9128b339140569e427fad44dc0a2f3058deaf0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-10-22 18:17:51 +08:00
parent 0bd7957468
commit 191d31cd12
4 changed files with 4 additions and 4 deletions
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2
include/configs/rk3288_common.h
View File

@ -25,7 +25,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00180000
#define CONFIG_SPL_TEXT_BASE 0x00000000
#define CONFIG_SPL_MAX_SIZE 0x100000
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define GICD_BASE 0xffc01000

2
include/configs/rk3328_common.h
View File

@ -20,7 +20,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SPL_TEXT_BASE 0x00000000
#define CONFIG_SPL_MAX_SIZE 0x100000
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */

2
include/configs/rk3368_common.h
View File

@ -28,7 +28,7 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x00000000
#define CONFIG_SPL_MAX_SIZE 0x60000
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
#define CONFIG_SPL_STACK 0x00188000

2
include/configs/rk3399_common.h
View File

@ -22,7 +22,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SPL_TEXT_BASE 0x00000000
#define CONFIG_SPL_MAX_SIZE 0x100000
#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x00400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */