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board: rockchip: rename rv1109 to rv1126 

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie5cec1508ec54e15b24909eafab275609de5adea
This commit is contained in:
Joseph Chen 2020-02-21 10:32:12 +08:00
parent e7c03ac680
commit 1633e8d278
9 changed files with 47 additions and 47 deletions
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8
arch/arm/dts/rv1109-evb.dts → arch/arm/dts/rv1126-evb.dts
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@ -4,12 +4,12 @@
*/
/dts-v1/;
#include "rv1109.dtsi"
#include "rv1109-u-boot.dtsi"
#include "rv1126.dtsi"
#include "rv1126-u-boot.dtsi"
/ {
model = "Rockchip RV1109 Evaluation Board";
compatible = "rockchip,rv1109-evb", "rockchip,rv1109";
model = "Rockchip RV1126 Evaluation Board";
compatible = "rockchip,rv1126-evb", "rockchip,rv1126";
};
&uart2 {

0
arch/arm/dts/rv1109-u-boot.dtsi → arch/arm/dts/rv1126-u-boot.dtsi
View File

22
arch/arm/dts/rv1109.dtsi → arch/arm/dts/rv1126.dtsi
View File

@ -3,7 +3,7 @@
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rv1109-cru.h>
#include <dt-bindings/clock/rv1126-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -12,7 +12,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "rockchip,rv1109";
compatible = "rockchip,rv1126";
interrupt-parent = <&gic>;
@ -81,7 +81,7 @@
};
grf: syscon@fe000000 {
compatible = "rockchip,rv1109-grf", "syscon";
compatible = "rockchip,rv1126-grf", "syscon";
reg = <0xfe000000 0x1000>;
};
@ -116,7 +116,7 @@
};
uart1: serial@ff410000 {
compatible = "rockchip,rv1109-uart", "snps,dw-apb-uart";
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff410000 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@ -128,7 +128,7 @@
};
pmucru: clock-controller@ff480000 {
compatible = "rockchip,rv1109-pmucru";
compatible = "rockchip,rv1126-pmucru";
reg = <0xff480000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
@ -136,7 +136,7 @@
};
cru: clock-controller@ff490000 {
compatible = "rockchip,rv1109-cru";
compatible = "rockchip,rv1126-cru";
reg = <0xff490000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
@ -154,7 +154,7 @@
};
uart0: serial@ff560000 {
compatible = "rockchip,rv1109-uart", "snps,dw-apb-uart";
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff560000 0x100>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@ -166,7 +166,7 @@
};
uart2: serial@ff570000 {
compatible = "rockchip,rv1109-uart", "snps,dw-apb-uart";
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff570000 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@ -178,7 +178,7 @@
};
uart3: serial@ff580000 {
compatible = "rockchip,rv1109-uart", "snps,dw-apb-uart";
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff580000 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@ -190,7 +190,7 @@
};
uart4: serial@ff590000 {
compatible = "rockchip,rv1109-uart", "snps,dw-apb-uart";
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff590000 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@ -202,7 +202,7 @@
};
uart5: serial@ff5a0000 {
compatible = "rockchip,rv1109-uart", "snps,dw-apb-uart";
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff5a0000 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;

42
arch/arm/include/asm/arch-rockchip/cru_rv1109.h → arch/arm/include/asm/arch-rockchip/cru_rv1126.h
View File

@ -4,8 +4,8 @@
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#ifndef _ASM_ARCH_CRU_RV1109_H
#define _ASM_ARCH_CRU_RV1109_H
#ifndef _ASM_ARCH_CRU_RV1126_H
#define _ASM_ARCH_CRU_RV1126_H
#include <common.h>
@ -26,8 +26,8 @@
#define HCLK_PDCORE_HZ (100 * MHz)
#define HCLK_PDAUDIO_HZ (150 * MHz)
/* RV1109 pll id */
enum rv1109_pll_id {
/* RV1126 pll id */
enum rv1126_pll_id {
APLL,
DPLL,
CPLL,
@ -36,21 +36,21 @@ enum rv1109_pll_id {
PLL_COUNT,
};
struct rv1109_clk_info {
struct rv1126_clk_info {
unsigned long id;
char *name;
bool is_cru;
};
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rv1109_pmuclk_priv {
struct rv1109_pmucru *pmucru;
struct rv1126_pmuclk_priv {
struct rv1126_pmucru *pmucru;
ulong gpll_hz;
};
struct rv1109_clk_priv {
struct rv1109_cru *cru;
struct rv1109_grf *grf;
struct rv1126_clk_priv {
struct rv1126_cru *cru;
struct rv1126_grf *grf;
ulong gpll_hz;
ulong cpll_hz;
ulong armclk_hz;
@ -60,7 +60,7 @@ struct rv1109_clk_priv {
bool set_armclk_rate;
};
struct rv1109_pll {
struct rv1126_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
@ -71,10 +71,10 @@ struct rv1109_pll {
unsigned int reserved0[1];
};
struct rv1109_pmucru {
struct rv1126_pmucru {
unsigned int pmu_mode;
unsigned int reserved1[3];
struct rv1109_pll pll;
struct rv1126_pll pll;
unsigned int offsetcal_status;
unsigned int reserved2[51];
unsigned int pmu_clksel_con[14];
@ -86,10 +86,10 @@ struct rv1109_pmucru {
unsigned int pmu_autocs_con[2];
};
check_member(rv1109_pmucru, pmu_autocs_con[1], 0x244);
check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244);
struct rv1109_cru {
struct rv1109_pll pll[4];
struct rv1126_cru {
struct rv1126_pll pll[4];
unsigned int offsetcal_status[4];
unsigned int mode;
unsigned int reserved1[27];
@ -116,7 +116,7 @@ struct rv1109_cru {
unsigned int autocs_con[26];
};
check_member(rv1109_cru, autocs_con[25], 0x584);
check_member(rv1126_cru, autocs_con[25], 0x584);
struct pll_rate_table {
unsigned long rate;
@ -134,10 +134,10 @@ struct cpu_rate_table {
unsigned int pclk_div;
};
#define RV1109_PMU_MODE 0x0
#define RV1109_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
#define RV1109_PLL_CON(x) ((x) * 0x4)
#define RV1109_MODE_CON 0x90
#define RV1126_PMU_MODE 0x0
#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
#define RV1126_PLL_CON(x) ((x) * 0x4)
#define RV1126_MODE_CON 0x90
enum {
/* CRU_PMU_CLK_SEL0_CON */

8
arch/arm/include/asm/arch-rockchip/grf_rv1109.h → arch/arm/include/asm/arch-rockchip/grf_rv1126.h
View File

@ -3,12 +3,12 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_GRF_RV1109_H
#define _ASM_ARCH_GRF_RV1109_H
#ifndef _ASM_ARCH_GRF_RV1126_H
#define _ASM_ARCH_GRF_RV1126_H
#include <common.h>
struct rv1109_grf {
struct rv1126_grf {
unsigned int soc_con0;
unsigned int soc_con1;
unsigned int soc_con2;
@ -200,6 +200,6 @@ struct rv1109_grf {
unsigned int usb_id_con;
};
check_member(rv1109_grf, usb_id_con, 0x1031c);
check_member(rv1126_grf, usb_id_con, 0x1031c);
#endif

6
board/rockchip/evb_rv1109/Kconfig → board/rockchip/evb_rv1126/Kconfig
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@ -1,13 +1,13 @@
if TARGET_EVB_RV1109
if TARGET_EVB_RV1126
config SYS_BOARD
default "evb_rv1109"
default "evb_rv1126"
config SYS_VENDOR
default "rockchip"
config SYS_CONFIG_NAME
default "evb_rv1109"
default "evb_rv1126"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y

2
board/rockchip/evb_rv1109/Makefile → board/rockchip/evb_rv1126/Makefile
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@ -4,4 +4,4 @@
# Copyright (c) 2019 Rockchip Electronics Co., Ltd
#
obj-y += evb_rv1109.o
obj-y += evb_rv1126.o

0
board/rockchip/evb_rv1109/evb_rv1109.c → board/rockchip/evb_rv1126/evb_rv1126.c
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6
configs/rv1109_defconfig → configs/rv1126_defconfig
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@ -1,11 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ROCKCHIP_RV1109=y
CONFIG_ROCKCHIP_RV1126=y
CONFIG_RKIMG_BOOTLOADER=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_TARGET_EVB_RV1109=y
CONFIG_DEFAULT_DEVICE_TREE="rv1109-evb"
CONFIG_TARGET_EVB_RV1126=y
CONFIG_DEFAULT_DEVICE_TREE="rv1126-evb"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y