From 14ce3c6d834c34a56549ecad1941573df2309264 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 27 Aug 2020 17:42:05 +0800 Subject: [PATCH] mtd: spinand: Support GD5F1GQ5UExxG Change-Id: I5f494ce09eed8c28bd2cb10bac5ec7d9113bac50 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/gigadevice.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index 7c978a6bc8..52a3766708 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -101,7 +101,7 @@ static int gd5f1gq4xexxg_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } -static int gd5f2gq4xexxg_ecc_get_status(struct spinand_device *spinand, +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, u8 status) { u8 status2; @@ -158,7 +158,16 @@ static const struct spinand_info gigadevice_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout, gd5f1gq4xexxg_ecc_get_status)), - SPINAND_INFO("GD5F2GQ4UExxG", 0x52, + SPINAND_INFO("GD5F1GQ5UExxG", 0x51, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout, + gd5fxgq5xexxg_ecc_get_status)), + SPINAND_INFO("GD5F2GQ5UExxG", 0x52, NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -166,7 +175,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout, - gd5f2gq4xexxg_ecc_get_status)), + gd5fxgq5xexxg_ecc_get_status)), SPINAND_INFO("GD5F2GQ4UBExxG", 0xd2, NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512),