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rockchip: rv1126: tpl: add ddr3 16bit support 

This patch auto detect BW16 constitute by byte0 and byte2 or
byte0 and byte3.

Change-Id: I22a8fa70db1d996573004320196c0892d5380f64
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping 2020-10-23 15:47:46 +08:00 committed by Jianhong Chen
parent 651b0d0dfc
commit 1040f70ad7
1 changed files with 17 additions and 2 deletions
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17
drivers/ram/rockchip/sdram_rv1126.c
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@ -2445,9 +2445,24 @@ static int sdram_init_detect(struct dram_info *dram,
u32 ret;
u32 sys_reg = 0;
u32 sys_reg3 = 0;
struct sdram_head_info_index_v2 *index =
(struct sdram_head_info_index_v2 *)common_info;
struct dq_map_info *map_info;
if (sdram_init_(dram, sdram_params, 0) != 0)
map_info = (struct dq_map_info *)((void *)common_info +
index->dq_map_index.offset * 4);
if (sdram_init_(dram, sdram_params, 0)) {
if (sdram_params->base.dramtype == DDR3) {
clrsetbits_le32(&map_info->byte_map[0], 0xff << 24,
((0x1 << 6) | (0x3 << 4) | (0x2 << 2) |
(0x0 << 0)) << 24);
if (sdram_init_(dram, sdram_params, 0))
return -1;
} else {
return -1;
}
}
if (sdram_params->base.dramtype == DDR3) {
writel(PATTERN, CONFIG_SYS_SDRAM_BASE);