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clk: rockchip: rk3568: support rkvdec clk setting 

Change-Id: Ic63b3c8ecbefcdf551d646ebb40521e6b521610b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2020-12-09 10:17:01 +08:00 committed by Jianhong Chen
parent a792c7e0c5
commit 0a04fb5062
2 changed files with 148 additions and 0 deletions
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18
arch/arm/include/asm/arch-rockchip/cru_rk3568.h
View File

@ -356,6 +356,24 @@ enum {
DCLK_EBC_SEL_CPLL_333M,
DCLK_EBC_SEL_GPLL_200M,
/* CRU_CLK_SEL47_CON */
ACLK_RKVDEC_SEL_SHIFT = 7,
ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT,
ACLK_RKVDEC_SEL_GPLL = 0,
ACLK_RKVDEC_SEL_CPLL,
ACLK_RKVDEC_DIV_SHIFT = 0,
ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT,
/* CRU_CLK_SEL49_CON */
CLK_RKVDEC_CORE_SEL_SHIFT = 14,
CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT,
CLK_RKVDEC_CORE_SEL_GPLL = 0,
CLK_RKVDEC_CORE_SEL_CPLL,
CLK_RKVDEC_CORE_SEL_NPLL,
CLK_RKVDEC_CORE_SEL_VPLL,
CLK_RKVDEC_CORE_DIV_SHIFT = 8,
CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT,
/* CRU_CLK_SEL50_CON */
PCLK_BUS_SEL_SHIFT = 4,
PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT,

130
drivers/clk/rockchip/clk_rk3568.c
View File

@ -2059,6 +2059,91 @@ static ulong rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
return rk3568_ebc_get_clk(priv);
}
static ulong rk3568_rkvdec_get_clk(struct rk3568_clk_priv *priv, ulong clk_id)
{
struct rk3568_cru *cru = priv->cru;
u32 con, div, src, p_rate;
switch (clk_id) {
case ACLK_RKVDEC_PRE:
case ACLK_RKVDEC:
con = readl(&cru->clksel_con[47]);
src = (con & ACLK_RKVDEC_SEL_MASK) >> ACLK_RKVDEC_SEL_SHIFT;
div = (con & ACLK_RKVDEC_DIV_MASK) >> ACLK_RKVDEC_DIV_SHIFT;
if (src == ACLK_RKVDEC_SEL_CPLL)
p_rate = priv->cpll_hz;
else
p_rate = priv->gpll_hz;
return DIV_TO_RATE(p_rate, div);
case CLK_RKVDEC_CORE:
con = readl(&cru->clksel_con[49]);
src = (con & CLK_RKVDEC_CORE_SEL_MASK)
>> CLK_RKVDEC_CORE_SEL_SHIFT;
div = (con & CLK_RKVDEC_CORE_DIV_MASK)
>> CLK_RKVDEC_CORE_DIV_SHIFT;
if (src == CLK_RKVDEC_CORE_SEL_CPLL)
p_rate = priv->cpll_hz;
else if (src == CLK_RKVDEC_CORE_SEL_NPLL)
p_rate = priv->npll_hz;
else if (src == CLK_RKVDEC_CORE_SEL_VPLL)
p_rate = priv->vpll_hz;
else
p_rate = priv->gpll_hz;
return DIV_TO_RATE(p_rate, div);
default:
return -ENOENT;
}
}
static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv,
ulong clk_id, ulong rate)
{
struct rk3568_cru *cru = priv->cru;
int src_clk_div, src, p_rate;
switch (clk_id) {
case ACLK_RKVDEC_PRE:
case ACLK_RKVDEC:
src = (readl(&cru->clksel_con[47]) & ACLK_RKVDEC_SEL_MASK)
>> ACLK_RKVDEC_SEL_SHIFT;
if (src == ACLK_RKVDEC_SEL_CPLL)
p_rate = priv->cpll_hz;
else
p_rate = priv->gpll_hz;
src_clk_div = DIV_ROUND_UP(p_rate, rate);
assert(src_clk_div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[47],
ACLK_RKVDEC_SEL_MASK |
ACLK_RKVDEC_DIV_MASK,
(src << ACLK_RKVDEC_SEL_SHIFT) |
(src_clk_div - 1) << ACLK_RKVDEC_DIV_SHIFT);
break;
case CLK_RKVDEC_CORE:
src = (readl(&cru->clksel_con[49]) & CLK_RKVDEC_CORE_SEL_MASK)
>> CLK_RKVDEC_CORE_SEL_SHIFT;
if (src == CLK_RKVDEC_CORE_SEL_CPLL)
p_rate = priv->cpll_hz;
else if (src == CLK_RKVDEC_CORE_SEL_NPLL)
p_rate = priv->npll_hz;
else if (src == CLK_RKVDEC_CORE_SEL_VPLL)
p_rate = priv->vpll_hz;
else
p_rate = priv->gpll_hz;
src_clk_div = DIV_ROUND_UP(p_rate, rate);
assert(src_clk_div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[49],
CLK_RKVDEC_CORE_SEL_MASK |
CLK_RKVDEC_CORE_DIV_MASK,
(src << CLK_RKVDEC_CORE_SEL_SHIFT) |
(src_clk_div - 1) << CLK_RKVDEC_CORE_DIV_SHIFT);
break;
default:
return -ENOENT;
}
return rk3568_rkvdec_get_clk(priv, clk_id);
}
#endif
static ulong rk3568_clk_get_rate(struct clk *clk)
@ -2183,6 +2268,11 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
case DCLK_EBC:
rate = rk3568_ebc_get_clk(priv);
break;
case ACLK_RKVDEC_PRE:
case ACLK_RKVDEC:
case CLK_RKVDEC_CORE:
rate = rk3568_rkvdec_get_clk(priv, clk->id);
break;
#endif
case ACLK_SECURE_FLASH:
case ACLK_CRYPTO_NS:
@ -2342,6 +2432,11 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
case DCLK_EBC:
rate = rk3568_ebc_set_clk(priv, rate);
break;
case ACLK_RKVDEC_PRE:
case ACLK_RKVDEC:
case CLK_RKVDEC_CORE:
rate = rk3568_rkvdec_set_clk(priv, clk->id, rate);
break;
#endif
case ACLK_SECURE_FLASH:
case ACLK_CRYPTO_NS:
@ -2610,6 +2705,38 @@ static int __maybe_unused rk3568_dclk_vop_set_parent(struct clk *clk,
return 0;
}
static int __maybe_unused rk3568_rkvdec_set_parent(struct clk *clk,
struct clk *parent)
{
struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
struct rk3568_cru *cru = priv->cru;
u32 con_id, mask, shift;
switch (clk->id) {
case ACLK_RKVDEC_PRE:
con_id = 47;
mask = ACLK_RKVDEC_SEL_MASK;
shift = ACLK_RKVDEC_SEL_SHIFT;
break;
case CLK_RKVDEC_CORE:
con_id = 49;
mask = CLK_RKVDEC_CORE_SEL_MASK;
shift = CLK_RKVDEC_CORE_SEL_SHIFT;
break;
default:
return -EINVAL;
}
if (parent->id == PLL_CPLL) {
rk_clrsetreg(&cru->clksel_con[con_id], mask,
ACLK_RKVDEC_SEL_CPLL << shift);
} else {
rk_clrsetreg(&cru->clksel_con[con_id], mask,
ACLK_RKVDEC_SEL_GPLL << shift);
}
return 0;
}
static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
{
switch (clk->id) {
@ -2625,6 +2752,9 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)
case DCLK_VOP1:
case DCLK_VOP2:
return rk3568_dclk_vop_set_parent(clk, parent);
case ACLK_RKVDEC_PRE:
case CLK_RKVDEC_CORE:
return rk3568_rkvdec_set_parent(clk, parent);
default:
return -ENOENT;
}