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clk: rockchip: rk3399: fix up the pll setting 

If the gpll and npll freq is no change,don't set pll once again.

Change-Id: Ib16a0a1ff56560997b6ed4b487fc2d56928c14ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-08-02 11:52:47 +08:00 committed by Kever Yang
parent efb944b698
commit 09e1ca4340
1 changed files with 12 additions and 1 deletions
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13
drivers/clk/rockchip/clk_rk3399.c
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@ -1158,6 +1158,12 @@ static void rkclk_init(struct rk3399_cru *cru)
* reset/default values described in TRM to avoid confusion in kernel.
* Please consider these three lines as a fix of bootrom bug.
*/
if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ)
rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg);
if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ)
return;
rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
@ -1218,8 +1224,13 @@ static void rkclk_init(struct rk3399_cru *cru)
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
rk_clrsetreg(&cru->clksel_con[21],
ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
(4 - 1) << ACLK_EMMC_DIV_CON_SHIFT);
rk_clrsetreg(&cru->clksel_con[22], 0x3f << 0, 7 << 0);
rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg);
}
static int rk3399_clk_probe(struct udevice *dev)