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dm: video: tegra124: Convert to livetree 

Update these drives to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Simon Glass 2017-07-25 08:30:01 -06:00
parent 000f15fa15
commit 079ff3b902
3 changed files with 11 additions and 25 deletions
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8
drivers/video/tegra124/display.c
View File

@ -12,7 +12,6 @@
#include <errno.h> #include <errno.h>
#include <display.h> #include <display.h>
#include <edid.h> #include <edid.h>
#include <fdtdec.h>
#include <lcd.h> #include <lcd.h>
#include <video.h> #include <video.h>
#include <asm/gpio.h> #include <asm/gpio.h>
@ -334,7 +333,6 @@ static int display_init(struct udevice *dev, void *lcdbase,
{ {
struct display_plat *disp_uc_plat; struct display_plat *disp_uc_plat;
struct dc_ctlr *dc_ctlr; struct dc_ctlr *dc_ctlr;
const void *blob = gd->fdt_blob;
struct udevice *dp_dev; struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1; const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */ int panel_bpp = 18; /* default 18 bits per pixel */
@ -363,9 +361,8 @@ static int display_init(struct udevice *dev, void *lcdbase,
return ret; return ret;
} }
dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev), dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
"reg"); if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__); debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL; return -EINVAL;
} }
@ -416,6 +413,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
debug("dc: failed to update window\n"); debug("dc: failed to update window\n");
return ret; return ret;
} }
debug("%s: ready\n", __func__);
return 0; return 0;
} }

3
drivers/video/tegra124/dp.c
View File

@ -10,7 +10,6 @@
#include <dm.h> #include <dm.h>
#include <div64.h> #include <div64.h>
#include <errno.h> #include <errno.h>
#include <fdtdec.h>
#include <video_bridge.h> #include <video_bridge.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch-tegra/dc.h> #include <asm/arch-tegra/dc.h>
@ -1572,7 +1571,7 @@ static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
{ {
struct tegra_dp_plat *plat = dev_get_platdata(dev); struct tegra_dp_plat *plat = dev_get_platdata(dev);
plat->base = devfdt_get_addr(dev); plat->base = dev_read_addr(dev);
return 0; return 0;
} }

25
drivers/video/tegra124/sor.c
View File

@ -7,9 +7,9 @@
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>
#include <errno.h> #include <errno.h>
#include <fdtdec.h>
#include <malloc.h> #include <malloc.h>
#include <panel.h> #include <panel.h>
#include <syscon.h>
#include <video_bridge.h> #include <video_bridge.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
@ -759,15 +759,12 @@ int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
const struct display_timing *timing) const struct display_timing *timing)
{ {
struct tegra_dc_sor_data *sor = dev_get_priv(dev); struct tegra_dc_sor_data *sor = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl; struct dc_ctlr *disp_ctrl;
u32 reg_val; u32 reg_val;
int node;
/* Use the first display controller */ /* Use the first display controller */
debug("%s\n", __func__); debug("%s\n", __func__);
node = dev_of_offset(dc_dev); disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
tegra_dc_sor_enable_dc(disp_ctrl); tegra_dc_sor_enable_dc(disp_ctrl);
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
@ -974,16 +971,13 @@ int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
{ {
struct tegra_dc_sor_data *sor = dev_get_priv(dev); struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE]; int dc_reg_ctx[DC_REG_SAVE_SPACE];
const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl; struct dc_ctlr *disp_ctrl;
unsigned long dc_int_mask; unsigned long dc_int_mask;
int node;
int ret; int ret;
debug("%s\n", __func__); debug("%s\n", __func__);
/* Use the first display controller */ /* Use the first display controller */
node = dev_of_offset(dc_dev); disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
/* Sleep mode */ /* Sleep mode */
tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
@ -1050,18 +1044,13 @@ static int tegra_sor_set_backlight(struct udevice *dev, int percent)
static int tegra_sor_ofdata_to_platdata(struct udevice *dev) static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{ {
struct tegra_dc_sor_data *priv = dev_get_priv(dev); struct tegra_dc_sor_data *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node;
int ret; int ret;
priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg"); priv->base = (void *)dev_read_addr(dev);
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC); priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
if (node < 0) { if (IS_ERR(priv->pmc_base))
debug("%s: Cannot find PMC\n", __func__); return PTR_ERR(priv->pmc_base);
return -ENOENT;
}
priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel", ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel); &priv->panel);